| Subject | Datestamp | Replies | Score | |||
|---|---|---|---|---|---|---|
| Re:Productivity applications et al | ||||||
| Re:More cores = good -- How about more FSBs | ||||||
| Re:Productivity applications et al | ||||||
| Re:PowerPC features | ||||||
| Re:New SSE4 instructions | ||||||
| New SSE4 instructions | ||||||
| Re:Documentation first! | ||||||
| Re:Cache Coherency in Dual Chip (8 Core) Core 2 | ||||||
| Re:VT-D Technology | ||||||
| Re:core naming convention | ||||||
| Re:How about both | ||||||
| Re:This is a tough area. | ||||||
| Re:My thoughts | ||||||
| Re:My Answers | ||||||
| Re:Memory mechanisms. | ||||||
| Re:My Answers | ||||||
| Re:Big L2 vs each core haveing it's own L2 + a Big | ||||||
| Re:alternative instruction sets | ||||||
| Re:Power consumptio vs Specialization | ||||||
| attached to Journal Discussion: Core Microarchitecture | ||||||