Dec Alpha was a Reduced Instruction Set Computer (RISC) that was "really" reduced and 64-bit. Alpha could not even load a single byte. String operations needed to load 8 bytes and the shift bits to extract individual bytes. The transistors Alpha saved by not decoding complex instructions were used to supply lots of registers. If I recall correctly, Alpha processors were not pipelined.
The original Alpha was pipelined with in-order execution. Later out-of-order execution was implemented.
Out-of-order execution is more complicated but *allows* higher clock speeds because it increases the allowable load-to-use delay, meaning that the first level cache does not have to be as fast for a given clock speed. Clock speed is limited by latency to the first level cache.
The lack of smaller than 32-bit operands ended up being a mistake, so later models added byte and word operands.
Transistors are more plentiful today but the waste of so many transistors delayed the Intel move to 64-bit by a decade and still hampers the architecture to this day.
Intel chose not to make a 64-bit x86 instruction set available in favor of their 64-bit Itanium processor. Their intention was to replace x86 with their IP protected Itanium, but AMD released AMD64 forcing Intel's hand.