Sure, very little current flows through the transistor's gate. But, the transistors themselves are imperfect switches, and so you get some current flowing from Vdd to Vss all the time anyway. For the products I tend to work on, around half or more of the power consumption comes from leakage, amazingly.
For the uninitiated: CMOS gates consist of a pair of complementary switches. One set connects Vdd (the positive voltage indicating a logic '1') to the output node, and the other set connects Vss or GND (the zero voltage indicating a logic '0') to the output node. The way CMOS works, there should only be one path from either Vdd or Vss to the output node. All other paths must be open.
The simplest example is an inverter. It has two switches. The switch from Vdd to output opens with the input is 1 and closes when the input is 0. The switch from Vss to output does the opposite: Closes when the input is 1 and opens when the input is 0.
CMOS burns power two main ways. The first and most obvious way is through switching, also called dynamic power. When the output goes to '1', the gate outputs a high voltage. This voltage then charges all of the gates connected to that output. Even if the gates don't leak, they still end up taking on a certain amount of charge due to their capacitance. The total charge taken on is V*C, where V is the voltage and C is the total capacitance of all the inputs this gate drives. Later, when the gate's output switches to 0, all that charge flows back out to ground. The more often you switch an output from 1 to 0, the more charge you ratchet from Vdd to Vss. Furthermore, while you're switching, there's often a very brief period when the two switches are both slightly closed. You can get some current racing directly from Vdd to Vss at this time.
The second, perhaps less obvious way CMOS burns power is through leakage. Modern transistors are far from perfect switches. When they're closed, they conduct, and when they're open they also conduct, just not as well. This leads to a phenomenon known as leakage. That is, even when the gates aren't switching, there's a constant current from Vdd to Vss, because the transistors haven't completely cut off the current flow. You can sometimes address this by lowering the input voltage or using transistors with different threshold voltages, but that trades off speed for leakage.
So, while the promise of CMOS is that no current flows when gates don't switch, the actuality is that tiny transistors in modern processes aren't as good at holding up to that ideal.