Comment Depends on the project (Score 4, Interesting) 25
When I was working in smaller analog ASICs we occasionally added pictures like these on the die. It sort of depends on the team and personality. In projects where the whole die was controlled by a small group (generally less than 10 people), you could do something like this. But recently working in teams where there are hundreds of people there are too many eyes scrutinizing every bit of space.
In addition, long ago, back on lower-end process nodes (eg. 0.25um+) there was not as hard requirements on density and fill. So it was easier to find open space on the die. But newer deep-submicron processes (anything below 40nm) has very strict requirements on density and fill. Usually any open space is back-filled with fill shapes to prevent problems in fabrication (shapes that are adjacent to large open spaces do not process equally to ones that are surrounded). So unless a section of the die is explicitly sectioned off, open areas are rare now.
Another thing that is very common is an area where you will see numbers/letters, usually a grid of them. What happens is each layer in the stack will get a letter or number such that they don't overlap each other. Later on if the die gets a mask update (this can happen if metal-changes are done to fix bugs/errors) then the layer identifier will get updated. So looking at the die you can identify which masks were used to make it. This is useful if you have multiple revisions of an otherwise identical product.
In college I also fabricated my own die through MOSIS for a research project (0.5um process IIRC). Of course when you control the whole die you can do anything you want, so I had to personalize it a bit.
An interesting one I saw once was a Pentium4 (I think). I had a bare die embedded in a clear keychain. Under the microscope they had a whole block sectioned off with what appeared to be the initials of everyone who worked on it. I sort of doubt Intel does that sort of thing anymore.