New Merced Patents

Intel and HP have been awarded 2 patents which reveal more about Merced. Speculatively executing both code paths originating at a conditional branch wastes resources which could be better used concentrating on one path. By applying speculative execution only when branch-prediction will probably fail, speculative execution is minimised to the cases where it will really help. In pretty much unrelated news, Intel's selling toys which might actually teach kids something.

REMOVE spec-exec and branch prediction.

[IGnatius T Foobar]

Apparently, Intel still doesn't know how to design a microprocessor. The design of IA-64 ought to be nothing more than a super-fast RISC core with the legacy IA-32 instruction set emulated in microcode. But apparently they're still wasting silicon on such silly crap as speculative execution and branch prediction. Duh.

Merced? oh ya, forgot.

[Maktoo]

Are they EVER going to ship IA-64??
Geez, it's just getting stupid. I wonder whether they're going to ship it first as a server-only type chip... (like they did with XEON)

Looks like they're going to spend so much time trying to do a decent job of emulating the x86 instructions that it's going to hamper the development of the rest of the chip.

Christ, if they just made a chip that was fast enough to do it they could just emulate x86 in software.... I'm sure it could do it now. At least then nothing would hold back future development

Whatever... i'm sticking with PowerPC.

REMOVE spec-exec and branch prediction.

[nekonoir]

[Cough!]
Methinks IA-64 is VLIW deep down

Yawn...Waiting for McKinley...HP at least have a clue about real processor design...
While we wait...Alpha or UltraSparc anyone?


Come the revolution ... we're going to need a bigger wall ...

Why remove speculative execution?

[slothbait]

What are you basing this on? Modern architectures have to have very deep pipelines (I think that the K7 will have 7) in order to maintain competitive speed. If it weren't for speculative execution, the processor would have to stall its pipeline every time a jump instruction was encountered. This is a rather serious performance hit, which would occur quite frequently in practice. I've never designed a processor myself, but according to all that I've read, neglecting speculative execution in this day and age is a rather Bad Idea.

Also: for what it's worth, the IA-64 is supposed to be a VLIW processor (or, as Intel calls it, EPIC), not a RISC design. These are more philosophies than set guidelines, however, so the matter is somewhat open to interpretation.

--Lenny

but wait...

[slew]

Hmm,

Almost all processors of the current generation have branch prediction (Alpha, HP, PowerPC, MIPS).

Many processors also have speculative execution.

Very few processors have microcode for most instructions.

Apparently nobody (but you) knows how to design a microprocessor ;^)

And yes, I have designed a microprocessor. Duh.

REMOVE spec-exec and branch prediction.

[Guy Harris]

ut apparently they're still wasting silicon on such silly crap as speculative execution and branch prediction.

...just like many other vendors of CPU for general-purpose computers. It's not as if Intel are the only folks on the planet doing speculative execution and branch prediction, which I guess means that, by your lights, the other vendors doing that don't know how to design microprocessors, either. Sic transit gloriaDigital^H^H^H^H^H^H^HCompaq, Sun, MIPS/SGI, HP, etc.

Perhaps they're all going in the wrong direction, but thumping only Intel for doing, say, branch prediction is an error, given that the folks I cited did it as well....

REMOVE spec-exec and branch prediction.

[Guy Harris]

And deep deep down the IA-64 IS RISC!

As opposed to on the surface, where it's something else?

Hmm... 41-bit opcodes.

[Mr Z]

From what I recall, "buckets" (which contain three instructions apiece) are 128 bits wide. If opcodes are 41 bits wide, I wonder what the other 5 bits are used for, and how.... (128 - (41*3)) == 5.

As for the branch predictor, it sounds somewhat interesting. The new part is the "predict that predictor is wrong." chuckle Talk about second-guessing...

The driblets about predication scheme sound bizarre, but then I'm probably tainted by the TMS320C6000-way of doing things...

REMOVE spec-exec and branch prediction.

[Mr Z]

This is ironic when you consider how much static prediction Merced relies on compilers to perform.

Is microcode dead? Dec Alpha

[Anonymous Shepherd]

Ummm
Isn't that description of a "super-fast RISC core with legacy IA-32 instructions set emulated in microcode" something similar to a Dec Alpha 21264 running at 500MHz and FX!32 or something?

Maybe its just 'or something'...
I do like Dec Alpha's style however, so I won't criticize you on that, but it isn't a waste to do spec-execution and branch pred, if it can get a greater than 50% success ratio... It really does speed up the CPU if a guess is correct.

Nice to see Intel get bogged by delays and screwups, however, as it gives AMD, PowerPC, and Digital Alpha room to shove and fight...

-Like my nick?
Anonymous Shepherd

Merced? oh ya, forgot.

[Maktoo]

Damn... clicked on the wrong button at the end of that comment....

That last line should read...

...MacOS X Server/LinuxPPC versus PC-based Linux and MacOS X/MacOS 8.x versus Windows 98/NT perspective.

Speculative execution is old!

[Kz]

How can they patent it? the PowerPC has it since the 604