Average Ratings 0 Ratings

Total
ease
features
design
support

No User Reviews. Be the first to provide a review:

Write a Review

Average Ratings 0 Ratings

Total
ease
features
design
support

No User Reviews. Be the first to provide a review:

Write a Review

Description

Creating designs at advanced process nodes necessitates a novel approach to place-and-route to handle the growing intricacies involved. Aprisa stands out as a detail-route-focused physical design platform tailored for contemporary SoCs. Operating as a complete RTL2GDSII solution, Aprisa facilitates digital implementation by providing comprehensive synthesis and place-and-route capabilities for both top-level hierarchical designs and block-level executions. Its alignment with signoff tools for STA timing and DRC offers tape-out quality correlation, which minimizes design closure challenges while ensuring peak performance, power efficiency, and area optimization (PPA). With its out-of-the-box performance, Aprisa enables physical designers to streamline each phase of the place-and-route process, accelerating their time-to-market. The unified architecture and shared analysis engines within Aprisa guarantee outstanding timing and DRC correlation throughout implementation stages and with signoff tools, significantly cutting down on the required flow iterations and engineering change orders (ECOs). As a result, this innovative approach ultimately enhances both productivity and design quality in complex projects.

Description

The Solido variation-aware design solutions, alongside IP validation, library characterization, and simulation technologies driven by cutting-edge AI, are utilized by thousands of designers at leading semiconductor firms across the globe. This integrated suite features AI-enhanced SPICE, Fast SPICE, and mixed-signal simulators that empower clients to significantly expedite crucial design and verification processes for advanced analog, mixed-signal, and custom IC designs. It delivers the industry's quickest and most thorough integrated IP validation solution, ensuring complete and seamless IP quality assurance from the design phase all the way to tape-out, encompassing all design perspectives and IP updates. Moreover, this comprehensive AI-driven design environment facilitates both nominal and variation-aware verification of custom IC circuits, achieving full design coverage with far fewer simulations while maintaining the accuracy comparable to brute-force methods. Furthermore, it offers rapid and precise library characterization tools that leverage machine learning for enhanced performance and reliability.

API Access

Has API No 

API Access

Has API No 

Screenshots View All

Screenshots View All

Integrations

No details available.

Integrations

No details available.

Pricing Details

No price information available.
Free Trial No 
Free Version No 

Pricing Details

No price information available.
Free Trial No 
Free Version No 

Deployment

Web-Based No 
On-Premises No 
iPhone App No 
iPad App No 
Android App No 
Windows Yes 
Mac No 
Linux Yes 
Chromebook No 

Deployment

Web-Based No 
On-Premises No 
iPhone App No 
iPad App No 
Android App No 
Windows Yes 
Mac No 
Linux Yes 
Chromebook No 

Customer Support

Business Hours Yes 
Live Rep (24/7) No 
Online Support Yes 

Customer Support

Business Hours Yes 
Live Rep (24/7) No 
Online Support Yes 

Types of Training

Training Docs Yes 
Webinars Yes 
Live Training (Online) No 
In Person Yes 

Types of Training

Training Docs Yes 
Webinars Yes 
Live Training (Online) No 
In Person Yes 

Vendor Details

Company Name

Siemens

Founded

1847

Country

United States

Website

eda.sw.siemens.com/en-US/ic/aprisa/

Vendor Details

Company Name

Siemens

Founded

1847

Country

United States

Website

eda.sw.siemens.com/en-US/ic/solido/

Product Features

Product Features

Alternatives

Alternatives

PathWave RFIC Design Reviews

PathWave RFIC Design

Keysight Technologies
Oasys-RTL Reviews

Oasys-RTL

Siemens
RFPro Circuit Reviews

RFPro Circuit

Keysight