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Average Ratings 0 Ratings

Total
ease
features
design
support

No User Reviews. Be the first to provide a review:

Write a Review

Description

Microwave Office facilitates the design of various RF passive components, including filters, couplers, and attenuators, along with active devices functioning under small-signal (AC) conditions, such as low noise and buffer amplifiers. Its linear configuration allows for the simulation of S-parameters (Y/Z/H/ABCD), small-signal gain, linear stability, noise figure, return loss, and voltage standing wave ratio (VSWR), complemented by features like real-time tuning, optimization, and yield analysis. Each E-series Microwave Office portfolio encompasses synchronous schematic and layout editors, 2D and 3D viewers, and extensive libraries featuring high-frequency distributed transmission models, as well as surface-mount vendor component RF models complete with footprints. Additionally, it offers measurement-based simulations and RF plotting capabilities. Microwave Office PCB further enhances the design process by enabling both linear and nonlinear RF circuit design through the advanced APLAC HB simulator, which provides powerful multi-rate HB, transient-assisted HB, and time-variant simulation engines for comprehensive RF/microwave circuit analysis. This extensive toolset empowers engineers to push the boundaries of RF design and streamline their development workflows effectively.

Description

ModelSim effectively simulates behavioral, RTL, and gate-level code, enhancing both design quality and debugging productivity through its platform-independent compilation. Its unique single kernel simulator technology allows for the seamless integration of VHDL and Verilog within a single design framework. This HDL simulator offers an unparalleled range of verification features at a competitive price, making it particularly suitable for the verification of small to medium-sized FPGA designs, especially those that are complex and mission-critical. ModelSim’s sophisticated code coverage tools yield essential metrics that aid in systematic verification processes. Additionally, its user-friendly design minimizes the obstacles to utilizing verification resources efficiently. All coverage data is securely stored in the highly efficient UCDB database, providing flexibility in how results can be accessed. Coverage outcomes can be analyzed interactively, either during or after simulation, including after merging results from multiple simulation sessions. This unified and easy-to-navigate environment equips FPGA designers with the necessary advanced tools for effective debugging and refinement of their projects.

API Access

Has API No 

API Access

Has API No 

Screenshots View All

Screenshots View All

Integrations

AWR Design Environment Platform Yes 
Siemens Precision No 
SystemC No 
Xilinx No 

Integrations

AWR Design Environment Platform No 
Siemens Precision Yes 
SystemC Yes 
Xilinx Yes 

Pricing Details

No price information available.
Free Trial No 
Free Version No 

Pricing Details

No price information available.
Free Trial No 
Free Version No 

Deployment

Web-Based No 
On-Premises No 
iPhone App No 
iPad App No 
Android App No 
Windows Yes 
Mac No 
Linux No 
Chromebook No 

Deployment

Web-Based No 
On-Premises No 
iPhone App No 
iPad App No 
Android App No 
Windows Yes 
Mac No 
Linux Yes 
Chromebook No 

Customer Support

Business Hours Yes 
Live Rep (24/7) No 
Online Support Yes 

Customer Support

Business Hours Yes 
Live Rep (24/7) Yes 
Online Support Yes 

Types of Training

Training Docs Yes 
Webinars Yes 
Live Training (Online) No 
In Person Yes 

Types of Training

Training Docs Yes 
Webinars Yes 
Live Training (Online) No 
In Person Yes 

Vendor Details

Company Name

Cadence Design Systems

Country

United States

Website

www.cadence.com/en_US/home/tools/system-analysis/rf-microwave-design/awr-design-environment-platform.html

Vendor Details

Company Name

Siemens

Country

United States

Website

eda.sw.siemens.com/en-US/ic/modelsim/

Product Features

PCB Design

3D Visualization No 
Autorouting No 
Collaboration Tools No 
Component Library No 
Design Rule Check No 
Differential Pair Routing No 
Schematic Editor No 

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