ModelSim Description
ModelSim simulates RTL and gate-level code. This increases design quality and productivity through platform-independent compilation. The single kernel simulator technology allows transparent mixing of VHDL with Verilog. ModelSim is a cost-effective HDL simulation that offers an unprecedented level in verification capabilities. It is ideal for verifying small and medium-sized FPGAs, especially those with complex, mission critical functionality. ModelSim's advanced coverage capabilities are valuable metrics for systematic testing. ModelSim is easy to use, which lowers the barrier to leveraging verification resources. All coverage data is stored in UCDB, a highly efficient database. Coverage results are available interactively, after simulation, or following a merging of multiple simulation runs. FPGA designers can debug their designs using an easy-to-use, unified environment.
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