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Average Ratings 0 Ratings

Total
ease
features
design
support

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Write a Review

Description

ChipMantra is an advanced cloud-based platform that utilizes AI to assist in the verification of semiconductors, specifically tailored for teams employing the Universal Verification Methodology (UVM). It is capable of processing RTL designs or pre-existing UVM verification environments for comprehensive analysis, while also facilitating workflows for the creation of reusable UVM components, including drivers, monitors, sequencers, agents, and scoreboards. The analysis capabilities include a thorough review of verification architecture and the health of testbenches, pinpointing potential coverage gaps, unaddressed scenarios, issues with assertions, and associated risks, all culminating in detailed verification reports. Targeted at verification engineers, hardware designers, and semiconductor teams involved in ASIC and system-on-chip projects, ChipMantra merges UVM environment generation with robust verification analysis. By integrating AI-assisted tools, ChipMantra empowers teams to enhance their existing design and verification workflows, ensuring a more efficient and effective verification process. This innovative approach not only streamlines workflows but also elevates the overall quality and reliability of semiconductor products.

Description

Advance your approach to RF simulation by focusing on the comprehensive design, analysis, and verification of radio frequency integrated circuits (RFICs). Gain assurance through the use of steady-state and nonlinear solvers for both design and verification processes. The availability of wireless standard libraries expedites the validation of intricate RFICs. Prior to finalizing an RFIC, it is essential to confirm IC specifications through RF simulation. These simulations take into account various factors such as layout parasitics, intricate modulated signals, and digital control circuitry. With PathWave RFIC Design, you can perform simulations in both frequency and time domains, facilitating seamless transitions between your designs and Cadence Virtuoso. Achieve accurate modeling of components on silicon chips, and enhance your designs using optimization techniques like sweeps and load-pull analysis. Integration of RF designs into the Cadence Virtuoso environment is streamlined, while the implementation of Monte Carlo and yield analysis can significantly boost performance. Additionally, debugging is made easier with safe operating area alerts, allowing for immediate utilization of cutting-edge foundry technology to stay at the forefront of innovation. This holistic approach to RFIC design not only improves efficiency but also elevates the overall quality and reliability of the final products.

API Access

Has API No 

API Access

Has API No 

Screenshots View All

Screenshots View All

Integrations

No details available.

Integrations

No details available.

Pricing Details

No price information available.
Free Trial Yes 
Free Version No 

Pricing Details

No price information available.
Free Trial Yes 
Free Version No 

Deployment

Web-Based Yes 
On-Premises No 
iPhone App No 
iPad App No 
Android App No 
Windows No 
Mac No 
Linux No 
Chromebook No 

Deployment

Web-Based Yes 
On-Premises No 
iPhone App No 
iPad App No 
Android App No 
Windows No 
Mac No 
Linux No 
Chromebook No 

Customer Support

Business Hours No 
Live Rep (24/7) No 
Online Support No 

Customer Support

Business Hours Yes 
Live Rep (24/7) No 
Online Support Yes 

Types of Training

Training Docs No 
Webinars No 
Live Training (Online) No 
In Person No 

Types of Training

Training Docs Yes 
Webinars Yes 
Live Training (Online) No 
In Person Yes 

Vendor Details

Company Name

BSC Global

Founded

2007

Country

Australia

Website

chipmantra.com

Vendor Details

Company Name

Keysight Technologies

Country

México

Website

www.keysight.com/us/en/products/software/pathwave-design-software/pathwave-rfic-design-software.html

Product Features

PCB Design

3D Visualization No 
Autorouting No 
Collaboration Tools No 
Component Library No 
Design Rule Check No 
Differential Pair Routing No 
Schematic Editor No 

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