ChipMantra Description

ChipMantra is an advanced cloud-based platform that utilizes AI to assist in the verification of semiconductors, specifically tailored for teams employing the Universal Verification Methodology (UVM). It is capable of processing RTL designs or pre-existing UVM verification environments for comprehensive analysis, while also facilitating workflows for the creation of reusable UVM components, including drivers, monitors, sequencers, agents, and scoreboards. The analysis capabilities include a thorough review of verification architecture and the health of testbenches, pinpointing potential coverage gaps, unaddressed scenarios, issues with assertions, and associated risks, all culminating in detailed verification reports. Targeted at verification engineers, hardware designers, and semiconductor teams involved in ASIC and system-on-chip projects, ChipMantra merges UVM environment generation with robust verification analysis. By integrating AI-assisted tools, ChipMantra empowers teams to enhance their existing design and verification workflows, ensuring a more efficient and effective verification process. This innovative approach not only streamlines workflows but also elevates the overall quality and reliability of semiconductor products.

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Company Details

Company:
BSC Global
Year Founded:
2007
Headquarters:
Australia
Website:
chipmantra.com

Media

A UVM agent containing Sequencer, Driver, and Monitor is connected by arrows to Sequence Items, a DUT Interface, and a DUT chip.

A UVM agent containing Sequencer, Driver, and Monitor is connected by arrows to Sequence Items, a DUT Interface, and a DUT chip.

A UVM agent containing Sequencer, Driver, and Monitor is connected by arrows to Sequence Items, a DUT Interface, and a DUT chip. A workflow diagram shows generated UVM passing through AI Validation and Self-Correction, validation checks, a self-correction engine, and verified UVM output. An AI Pipeline diagram connects a central AI chip and database to inputs including Knowledge Base, Design Specs, Verification History, Domain Expertise, and Reusable Assets, and to AI orchestration functions. An RTL/design specification code panel feeds an AI chip, which outputs checked UVM components: Driver, Monitor, Sequencer, Agent, Environment, Scoreboard, and Test. A Verification Plan display shows a verification flow from input analysis through test-scenario generation, coverage planning, and risk analysis, plus test-progress and coverage-target charts. A central AI chip is connected to labeled verification components including Sequencer, Driver, Monitor, Scoreboard, Config DB, Objects, TLM Connections, Virtual Sequence, Callbacks, and Phases, with architecture and analysis panels above.
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