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ease
features
design
support

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Description

Certified by Foundry, the AFS Platform provides nm SPICE accuracy, achieving speeds five times greater than conventional SPICE and more than twice as fast as parallel SPICE simulators. It stands out as the quickest nm circuit verification platform suitable for analog, RF, mixed-signal, and custom digital circuits. The latest addition of eXTreme technology enhances its capabilities. Specifically designed for large post-layout circuits, the AFS eXTreme technology accommodates over 100 million elements and operates three times faster than typical post-layout simulators. It is compatible with all leading digital solvers. With its top-tier usability, the platform maximizes the reuse of existing verification infrastructures, while its advanced verification and debugging features significantly enhance verification coverage. This results in improved design quality and reduced time-to-market. The platform guarantees SPICE accuracy and offers high-sigma verification, being a staggering 1000 times faster than brute-force simulation methods. It is user-friendly and easy to deploy, with access to AFS eXTreme technology provided at no extra cost; thus, it represents a comprehensive solution for modern circuit verification needs.

Description

Oasys-RTL meets the demand for enhanced capacity, quicker runtimes, elevated quality of results (QoR), and physical awareness by performing optimization at a more abstract level while also incorporating integrated floorplanning and placement features. This tool significantly improves the quality of results by facilitating physical accuracy, efficient floorplanning, and rapid optimization cycles, ensuring timely design closure. Its power-aware synthesis capabilities encompass support for multi-threshold libraries, automatic clock gating, and a UPF-based multi-voltage domain flow. During the synthesis process, Oasys-RTL intelligently inserts the necessary level shifters, isolation cells, and retention registers according to the power intent specified in the UPF framework. Additionally, Oasys-RTL can generate a floorplan directly from the design's RTL by applying dataflow and adhering to timing, power, area, and congestion constraints. It adeptly incorporates regions, fences, blockages, and other physical directives via advanced floorplan editing tools while automatically positioning macros, pins, and pads to optimize the layout. This holistic approach ensures that designers can efficiently manage complex designs and meet stringent performance requirements.

API Access

Has API

API Access

Has API

Screenshots View All

Screenshots View All

Integrations

No details available.

Integrations

No details available.

Pricing Details

No price information available.
Free Trial
Free Version

Pricing Details

No price information available.
Free Trial
Free Version

Deployment

Web-Based
On-Premises
iPhone App
iPad App
Android App
Windows
Mac
Linux
Chromebook

Deployment

Web-Based
On-Premises
iPhone App
iPad App
Android App
Windows
Mac
Linux
Chromebook

Customer Support

Business Hours
Live Rep (24/7)
Online Support

Customer Support

Business Hours
Live Rep (24/7)
Online Support

Types of Training

Training Docs
Webinars
Live Training (Online)
In Person

Types of Training

Training Docs
Webinars
Live Training (Online)
In Person

Vendor Details

Company Name

Siemens

Founded

1847

Country

United States

Website

eda.sw.siemens.com/en-US/ic/analog-fastspice/

Vendor Details

Company Name

Siemens

Founded

1847

Country

United States

Website

eda.sw.siemens.com/en-US/ic/oasys-rtl/

Product Features

Product Features

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