SiLogy Description
Our next-generation platform enables chip developers and verification engineers design and debug 10x quicker. Verilator allows you to run thousands of parallel tests at the touch of a button. Share test results and waveforms seamlessly with anyone in your company, tag coworkers on signals and track test and regression errors. Verilator is used to distribute test runs and Dockerized simulation binaries across our compute cluster. We collect the log files, results, and optionally rerun failed tests to generate waveforms. Docker allows us to ensure that our test runs are consistent, reproducible and repeatable. SiLogy increases chip developer productivity by enabling faster debugging and design times. Before SiLogy the only way to debug a failing test was by copying lines from logs, debugging using waveforms on local machines, or rerunning simulations that could take days to run.
SiLogy Alternatives
PathWave RFIC Design
Beyond traditional RF simulation, design, analyze, verify radio frequency integrated circuits. Design and verification can be done with confidence using both nonlinear and steady-state solvers. Complex RFICs can be validated faster using wireless standard libraries. Verification of IC specifications via RF simulation must be done before taping out an RFIC. Simulators can simulate the effects of layout parasitics, complex modulated signal, and digital control circuitry. PathWave RFIC Design allows you to simulate in both frequency and time domains and can bring your designs to Cadence Virtuoso. Simulate components on silicon chips accurately. Optimize designs using sweeps and load-pull analysis. Incorporate RF designs into the Cadence Virtuoso environment. Performance can be increased with Monte Carlo and yield analysis. Safe operating area warnings simplify debugging. Use the most recent foundry technology right away.
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Ansys Exalto
Ansys Exalto, a post-LVS RLCk extractor software solution, allows IC designers to capture unknown crosstalk between different blocks in their design hierarchy. It extracts lumped-element parasitics from the design hierarchy and generates an accurate model for electrical and magnetic coupling. Exalto interfaces well with most LVS tools, and can be used in conjunction with the RC extraction tool you choose. Ansys Exalto post LVS RLCk extraction allows IC designers to accurately predict electromagnetic and substrate-coupling effects for signoff on circuits previously "too large to analyze." The extracted models can be back-annotated to any schematic or netlist and support all circuit simulators. Modern silicon systems have seen a rise in RF and high speed circuits. This has made electromagnetic coupling a first-order effect that must be accurately modelled to ensure silicon success.
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Analog FastSPICE Platform
The AFS Platform is foundry-certified and delivers SPICE accuracy of nm, 5x faster than traditional simulations, and >2x faster compared to parallel SPICE simulators. The fastest nm platform for circuit verification of analog, RF and mixed-signal circuits. Now includes the new eXTreme Technology. AFS eXTreme is 3x faster and has a 100M element capacity for large post-layout circuits. Supports all leading solvers. Best-in class usability allowing maximum reuse and reuse of verification infrastructure. Verification coverage is improved by advanced verification and debugging capabilities. Improved design quality and reduced time to market. SPICE high-sigma accuracy. 1000x faster than brute force simulation Easy to use and deploy. AFS eXTreme is available for no additional charge.
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Tessent
Reduce design complexity with high-quality DFT. Tessent silicon management solutions include advanced features for debugging, safety and security, and in-life analytics to meet today's evolving silicon lifecycle challenges. Create an infrastructure to make designs more testable. Silicon lifecycle management solutions enable high-quality testing, identify defects and hidden limiters of yield, and go beyond test to system debugging, validation, and validation. This ecosystem of tools analyzes data in order to provide critical insights into the system that can be used for monitoring. Best-in-class DFT, debug and in-life monitoring solutions, combined with powerful data analytics, will ensure the highest test quality and accelerate yield ramp. They will also improve safety, security and reliability throughout the silicon lifecycle. Reduce time to yield, manage production excursions, and recover the yield caused by systematic defects.
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Integrations
Company Details
Company:
SiLogy
Year Founded:
2023
Headquarters:
United States
Website:
silogy.io
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Product Details
Platforms
SaaS
Type of Training
Live Online
Customer Support
Online
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