Comment: Both Suck (Score 1) 301
Both languages are old and the tools you have to deal with are incredibly complicated. I really don't think it will matter which you pick (I personally see Verilog used more in universities, but that doesn't make it the right choice).
What you do need to worry about is coding style. Most students learning an HDL for the first time will come in with programming experience. They're going to try to use programming constructs and loops that, while appropriate for normal code will not represent synthesizable hardware.
With that in mind you need to pound style rules into their heads. Since one of primary functions of each language is simulation (as opposed to synthesis) using legal code may lead you into trouble. Get around this by enforcing strict style rules. Example set of Verilog rules: http://www.eecs.umich.edu/eecs/courses/eecs470/tools/verilog_guidelines.pdf [eecs.umich.edu copied from C. E. Cummings, âNonblocking Assignments in Verilog Synthesis, Coding Styles That Kill,â SNUG 2000. (http://www.sunburst-design.com/papers/CummingsSNUG2000SJ NBA.pdf))
Every time you code remind yourself "I am writing hardware".
