CMOS technology, is static meaning that there is no current flow through a gate when it is on or off. Current only flows while the transistor is transitioning states.
That's the idea but it has never quite worked that way. There is always a small current flow from vdd to ground even when the gate is "off". At smaller geometries, this leakage becomes not just significant but can be the majority of the power drain. Thus, having lots of cores ready but not active does not help. They still suck power. Finfets help a great deal but only for a while and at 14nm and below the problem is coming back. The work around is to actually turn off the power to inactive regions. This works but shutting down and restarting units is complicated and time consuming, making it more difficult to respond to transient demands.