Actually, it's 40 chips for 640MB on a DIMM. The sample they demonstrated was 10GB in total.
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I've spent all of two days now reading about PCM, but here's an observation: The lessons learned in making NAND flash work as a high-speed storage medium are applicable here as well. Many of the problems are the same, with the need for wear-leveling and optimization of write performance. The solutions appear to be somewhat different though. Their wear-leveling algorithm does not at all resemble the complexity of a typical FTL and I think that's the point.
Dealing with the problems of getting this technology to scale are simpler and cheaper to address than those presented by NAND flash, if only because in-place writes are now back on the table, with no erase-before-write cycle. This technology looks like it needs to ramp up in density though before it's a viable alternative to current NAND flash. 40 chips for 10GB on a DIMM is not going to get much done inside a 2.5" SSD case.
I also did not think their comparison to PCIe-based SSDs was fair. They called these 'state of the art', when the best SSDs are currently designed around use over a SATA3 bus and have performance figures much higher than those quoted.