Comment Re:Layout by HAL (Score 1) 178
well a cpu with a 1GHz clock has 1nS to process data between flops - yes it's a bit like laying out microwave stuff -but in the very small - what happens is that it all starts with some layout person/people creating a standard cell library, they'll use spice to simulate and characterise their results - they'll pass this to the synthesis/layout tool makes a good first guess, they'll add in some fudge factor - then a timing tool looks at the 3d layout and extracts real timing, including parasitics to everything in 3-space around a wire - they check - does the timing from every flop to every other flop through every possible path meet both setup and hold times for the destination flop - if it does you're golden, tape it out - if not tweak something or resynthsise a block with tighter constraints etc etc
There is very complex delay analysis done - in all corners of the underlying fab process - automated layouts seldom look "pretty" at least from the point of hand done boards