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Comment Re:bc trim is application- dependant. Their assump (Score 1) 66

And the native cell endurance has very little to do with it.
Erase block size is more important. As well as over-provisioning.

They don't go in to details, but if they can re-purpose a MLC cell as SLC after it has worn out too much to function as MLC, that's going to increase the drive endurance/decrease amount of required over provisioning.

Comment Re: Lifetime at 16nm? (Score 2) 66

All of those questions are about the controller and it's wear levelling software, not the flash chips.
In regards to your questions about security, the specific number of times a cell can be erased is irrelevant, only that wear level takes place and physical data is moved around to different locations and not immediately (or potentially, ever) erased from the old location.

In theory, you should just need to delete the encryption key, because the controller encrypts all the data on the flash chips 256bit AES encryption. Again, that's entirely in the controller software.

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