Comment Re:Deja vu all over again (Score 1) 112
there is a linear relationship between code density and the functional bandwidth of the instruction caching at every level.
Even if this were true (which it isn't), and even if you were right that CISC has twice the code density of RISC (which it doesn't), it would still be a long way short of proving your claim that CISC gives better performance than RISC.
I don't presume to understand why ARM do what they do.
Certainly not 2X, that was normal slashdot hyperbole. 1.2-1.5X depending on what you compare with. But you are putting words in my mouth. Nowhere did I claim RISC was better than CISC or visa versa in any general sense. I said that compact instruction encodings are better than inefficient instructions encodings, which they clearly are for a broad class of CPU memory hierarchies that have been around in recent years. The decoding benefits of RISC were tangible for 1990 era CPUs, but the decoding overhead hasn't changed, while the rest of the CPU has got much bigger. So the decoding overhead is now negligible for the CPUs we put in phones and PCs, while the instruction bandwidth has a bottom line effect on performance. You can address it with wider buses and bigger caches, but then you can have wider buses and bigger caches with smaller instructions too.
I'm not seeking to prove a claim. It's just the way things are.
Accordingly a CPU with a real Huffman coded instruction set might be even better. Feel free to go implement one.
I don't need to presume, I know that they removed some complex instructions because they made the hardware more complex and reduced performance.
Which contradicts the evidence of the vast majority of CPUs ever made, which is they get faster as you throw more gates at them.