• VHDL's strong typing will cause you hours of lost work because of silly things like the differences between std_logic_vector and unsigned. Others claim this is a feature as it prevents bugs due to type conversions. This should be a non-issue when using Verilog as your test suite should test everything. Plus decent simulators/synthesis tools have lint functions.
• VHDL is far too verbose. It requires replicating the entity definition before instancing it. Now when you change ports(and large designs will require MANY port changes) you get to change them in 3 places instead of 2. In ASIC applications, netlist brevity becomes very important when gate-level fixes need to be made.
• Many tools do not like VHDL. At least two that I know of require compiling libraries first. With Verilog you can usually just throw a bunch of files at them and the tool can elaborate the design. In ASIC development, you very well may use 5-6 tools other than the simulator and synthesis tool.
• SystemVerilog is a train wreck, but is advancing Verilog adoption.

You may want to consider schematic entry if your design is simple enough. At the very least, look at the floorplan of your synthesized designs so you can how much logic it took for each module.