I work at a chip company doing ASIC and custom SOC microprocessor stuff. We mostly use verilog here for our stuff. Most of the VHDL I see comes from customers, which often gets blended into our verilog platforms. All our RTL IP cores are verilog that I know of, at least that I've used/seen, and our integration work to make platforms out of all the IP pieces is verilog. What we synthesize to gates is also a verilog gates netlist result that goes to place/route into silicon.
In college the class I took that involved this sort of thing was in VHDL, and I hated that. had me really nto wanting to do this kind of work, I was really happy when I was exposed to verilog and I didn't hate it, and I've been a chip guy for over 10 years now.
But as I understand, VHDL is far more popular in some locations, and verilog in others, so jobs in other locales may be completely opposite to my work environment. It would probably be nice to show some of each to be a little familiar with both such as comparing/contrasting = to = and == to ===, but focus on one or the other for people to really get experience fitting pieces together and learning the general stuff about RTL design, etc. that are not as dependent on what language you use.