Comment Re:And yet IBM soldiers on... (Score 1) 156
The x86 decoder is as large as an entire ARM execution core, and what's more it makes the pipeline and branch prediction a lot more complex with the variable length instructions so necessitates yet more complexity. From an asm point of view (and probably the compiler writer's point of view), a modern RISC processor is simpler to write software for than CISC, things like having all the ALU instructions taking 3 operands, having 32 registers that are truly general purpose (x86 still has some instructions that only work with certain registers) etc. RISC is a bit of a misnomer too. There are CISC chips with fewer instructions than some RISC chips, in reality RISC should be called load and store since that's the main differentiator: ALU instructions on RISC only work on registers and immediate values (which makes the chip a lot simpler to implement), whereas CISC chips often have all sorts of addressing modes for ALU instructions.