Comment Re:OK, I'll Say It (Score 1) 140
If your order volume is small, the fixed costs will eat you alive.
...which is why opencores is asking for donations
There is a block level view of what's going in, which is mostly off-the-shelf OpenCores cores, but there are no detailed plans about how this is going to be translated into an actual ASIC design.
1. Push ASIC button
2. Profit
Just kidding
There are only plans for making a FPGA based development platform.
Don't get me wrong, a FPGA platform is a good thing to do. A project like this won't have the resources to do very much design validation through simulation (which requires lots of people writing tests and running sims, i.e. real money), so FPGA based prototyping and validation is even more important than it is for conventional "closed source" ASIC projects. However, there is no plan given for how they're going to take their working FPGA design and turn it into an ASIC design.
Verification is always the largest issue when you are building complex systems. One of the benefits of open source however, is that someone might have done it before you. In the case of the OpenRISC CPU, the 80000 (correct me if I'm wrong) regression tests of GCC is being used as one source of verification stimuli. Keep in mind also that the design isn't being created from scratch. The core is about ten years old
It's somewhat revealing that they're using a single small Altera Cyclone IV FPGA (under $60 qty 1 through Digikey). If you don't understand the significance, this means their design is tiny and trivial and low tech by current standards.
This isn't an effort to create the next-generation-273-bit-mega-hyper-threaded-with-DDR-5-and-379-core-subpixel-shader-gpgpu on crack. It's a fairly standard 32 bit RISC SoC, with the main difference that the RTL code is open source, and that the ASIC will be sold at a low cost even in low quantities. Think of how popular the Arduino platform is for example. It has some extra street cred, because the layout is open source. Now this is taken one step further, by using a LGPL:d CPU and peripherals. The quaking-in-their-boots part sounds a bit exaggerated, but still, it is primarily because this hasn't been done before. And if it turns out good, there is an ASIC proven SoC that can be modified and recreated by anyone that doesn't want to pay an ARM or a MIPS license for a 32-bit RISC system. Also, by using a fairly cheap FPGA, a reference board with either the ASIC or the FPGA can be sold at a reasonable cost.