MinSoC support even more boards (http://opencores.org/project,minsoc) but there are less supported peripherals there. Ethernet and UART IIRC
The cheapest ones are about $50 or $60. Think the de0-nano is cheapest
If you want to try out some OpenRISC developing without having to buy a dev board, there is also the OpenRISC architecture simulator or1ksim http://opencores.org/or1k/Or1ksim It supports UART through xterm or telnet, ethernet with TUN/TAP and a framebuffer
Or simply the dude who did it owned a DSP1800 as opposed to the board I have at home?
You're actually spot on
I think it was a tight fit though, so I'm not sure it will fit on smaller spartan 3 FPGAs. Disabling caches and hardware mul/div and stuff like that could help. It's a pretty common board, so if anyone is interested in trying, just drop in to #opencores on freenode and chat with us
CPU implementations, in this case, are far from what they could be. Why is there not an open source equivalent of ARM's processors in the way that the Linux kernel was developed due to a lack of other open OS kernels? There's actually a couple of good reasons, but none should be terminal to the idea.
I'm working on the OpenRISC project. That is 100% LGPL and with Linux 3.1 it will be supported in the mainline kernel (along with an ever increasing support for different RTOS's). We are slowly getting there
Timing errors are always the hardest things to track down. Fortunately we are talking about a fully digital ASIC with one clock domain, except for the memory controller, and some other things I might have ignored. I recently finished a project where we converted a FPGA to an ASIC that had more than 180 clock domains. That, my friend, was hard.
The logic bugs are mostly tracked down in simulation, and on the FPGA prototypes. Remember that the openRISC CPU has been available for some time already, runs Linux 2.6.38 fine and is being used in the industry. The RTL is mostly done except for ASICification of some parts.
The fear of suppliers running out of MCUs is real, I can tell you. Reverse-engineering of chips, and reimplementation in FPGA happens all the time in the industry. It is expensive and time-consuming, so having the source code and constraints around is a big help.