The discussion was about adding more registers in a CISC architecture, and so CISC functionality is the context.
"CISC functionality" is the ability to execute a given CISC instruction set with acceptable performance. Transistors can be used in several different ways to achieve that, and you can choose to use fewer transistors in one place on a chip in favor of more transistors in another place, and if that choice means you still get better overall performance executing the same instruction set, that choice is a good one.
When you ask what "the same functionality means" that is absurd. You can't implement a subset of the functionality and still have the same functionality.
Again, as long as the full instruction set can be executed (even if some of it is executed by trap code), you don't have a subset. You may happen to execute some functions slower, and other functions faster, but if the net result is faster execution of the code actually run on the machine, you have a better implementation.
I'll put this in simpler terms. Smart people design CPUs and they don't add a bunch of registers even though that would be useful.
Smart people add registers iff they're sufficiently useful that it's worth either increasing the die size or taking transistors away from other functions.
The reason they don't do it is because of the additional chip real estate it would cost in an already over-taxed landscape, not because they are lazy or haven't though of the idea.
For existing architectures, the reason they don't do it is that it would require changes to the instruction format, which, for most instruction set architectures, would be a royal pain. For x86, they (AMD, to be specific) could and did add Yet Another Prefix to double the number of registers as the instruction set already had a tradition of adding prefixes. For ARM, they were already introducing a 64-bit variant of the instruction set, and didn't have to maintain binary compatibility. For, for example, System/3x0, you'd have to add prefixes to an instruction set lacking prefixes, or somehow use opcode bits to refer to additional registers. If somebody were to design a brand new CISC architecture (in an era where we're not designing many new instruction set architectures at all), they could design one with 32 GPRs.