Next Gen Intel CPUs Move To Yet Another Socket 254
mr_sifter writes "According to a leaked roadmap, next year we'll be saying hello to LGA1155. The socket is 1-pin different from the current LGA1156 socket Core i3, i5, and some i7s use. Sandy Bridge CPUs will be based on the current 32nm, second-generation High-k metal gate manufacturing process. All LGA1155 CPUs will have integrated graphics built into the core instead of a separate chip. This is an upgrade from the current IGP, PCI Express controller and memory controller in Clarkdale CPUs. which is manufactured on the older 45nm process in a separate die (but still slapped together the same package). This should improve performance, as all the controllers will be in one die, like existing LGA1366 CPUs."
Re:Figures... (Score:5, Informative)
And yet,... (Score:5, Informative)
...the AM2+/AM3 socket on my AMD board continues to be useful for new AMD CPUs literally years after I originally purchased it.
Re:Integrated graphics in the CPU? (Score:4, Informative)
Your point would have been valid 10 years ago but the die area used for the CISC instruction decoder on a modern x86 processor is negligible. Infact the x86 instruction set is more compact than a pure RISC cpu so you can fit more instructions into the instruction cache (ARM processors have a THUMB mode with more compact 16bit instructions because of this).
Re:Figures... (Score:4, Informative)
Only because Intel chooses to obsolete old chipsets (or, more preciselly, arbitrarily changes bus specs on new motherboards - I've seen an ASRock one for C2D with i865). AMD somehow manages to keep latest versions of their CPU interconnect backwards compatible...you really want to say Intel isn't capable of doing so? (especially if Intel simply uses PCI Express for those chips, which is explicitly backwards compatible)
Re:Integrated graphics in the CPU? (Score:5, Informative)
The key is modern RISC, not RISC. x86 is horribly inefficient. I'm not talking about the instruction decoder, I'm talking about the instruction semantics. x86 was never designed for today's high-performance CPUs, and the result is that the instruction set basically allows the programmer to do anything they want, even if it goes against modern CPU design optimizations. This forces the CPU to devote a large amount of die area to workaround logic that detects the thousands of possible dirty tricks that a programmer might use which are allowed by the ISA. For example, every modern RISC requires that the programmer issue cache flush instructions when modifying executable code. This is common sense. x86 doesn't, which means there needs to be a large blob of logic checking for whether the data you just touched happens to be inside your code cache too. The fact that on x86 you can e.g. use one instruction to modify the next instruction in the pipeline is just so ridiculously horribly wrong it's not even funny. There are similar screw-ups related to e.g. the page tables. I can't even begin to imagine the pains that x86 CPU engineers have to go through.
You can make an x86 chip reasonably small and very slow, or very large and very fast. x86 doesn't let you have it both ways to any reasonable degree.
Re:Sigh (Score:3, Informative)
Intel, through illegal practises, prevented AMD from benefiting fully from their lead with K7 and early K8 Athlons. This illegally rerouted money weakened AMD R&D and fabs, while strenghtening Intel ones at the same time.
Re:And yet,... (Score:4, Informative)
...the AM2+/AM3 socket on my AMD board continues to be useful for new AMD CPUs literally years after I originally purchased it.
Intel had a long run with the Socket 775 boards, and AMD pulled this stunt back with their Socket 939 to AM2 upgrade. AM2 is a 940 pin socket.
I do agree AMD did something right with their AM2, AM2+, AM3 sockets being interchangeable for many CPUs. Just some of the more interesting features get disabled when running an AM3 cpu on an AM2 socket.