What they did was completely insane, but possibly not bullshit. This topic is covered in better detail at
and they're not bullshit artists, though anything is technically possible.
Most modern process technologies run on either 12" or 18" wafers. I don't know what the wafer map looks like and I'm too lazy to do the geometry, but it may literally be one die off a wafer at that size.
The things that would concern me personally as a former lead ASIC designer are:
- Design - over that kind of silicon area, how many possible clock domains and PLLs do they have? There'd have to be a lot of clock domains asynchronously latching data because even at low speeds you'd have enough clock skew to choke a blue whale. And what tool could actually place and route and what kind of memory/CPU did it have? How was power and signal integrity closed at this scale as well? And what type of front-end and back-end back-annotated simulation did they conduct, or was this all reliant on formal verification + static timing analysis? I'm even curious how long physical design and design-rule checks took on this.
- Testability - in several respects, this is a monster to test, so how long does scan/BIST/memBIST take to run, what kind of probe card and load board was designed to test this at "wafer sort" (and I use that term loosely), and how do they deal with things like gross IDD (i.e. dead shorts between power and ground)? I get that they have some kind of built-in self-repair, but one gross IDD failure and you're literally cooked. Yields must be utterly dreadful even with a stable process at a Tier 1 fab.
- Packaging - again in several respects, including how was the packaging designed, what type of I/O and power distribution scheme was used (at 15kW no less!). I'd also be really concerned about what type of heat dissipation at that much power they have, and how they prevent warping of the package substrate because of thermal differences across the area of the die/package. Is this even possible with FR4 or did they go to PTFE or some other material? Same with once it's placed on a board.
- Product - what kind of I/O is this thing supporting? How many layers of PCB did they use for this? What actually feeds this thing data coherently? Where does it all go?
Bluntly, that's a lot of questions. The fact that nobody heard anything about this up to now may be a factor of NDAs, but this monstrosity is so beyond the pale from a design perspective that I don't know that I could take someone seriously if they even told me to work on this. Again, I'm not saying it's impossible, but I'm saying that truly nothing like this has ever been attempted, and I would be much more reliant on a subdivided design with fast interconnect even when they're talking about the type of computing problem they're trying to solve. Let's see the package alone, and it'll answer some more questions for us.