The price has nothing to do with the lack of leverage for the fab. In semiconductors, there has been a massive consolidation of vendors as tools become more and more specialized (and thus far more expensive to design).
For example if you want to buy an immersion ArF lithography tool, you have exactly two vendors to choose from. Both 1 2 of these vendors will charge you tens of millions of dollars for a single tool, and both will make no promises about software upgrades, unless you pay for a service contract.
At the next generation if you want to buy an EUV lithography tool, you have exactly one vendor, with a nice long waiting list (of your competitors) to get a tool. So good luck trying to negotiate on the software patches for the PC attached to it. Also the last quote I heard about for one of these tools was actually over 100 Million USD.
Also more to the point of the article, if you are doing inspections for 12 hours in a row on anything complex, you will suck as an inspector and I would hope Samsung would not accept this as a practice in China (or anywhere for that matter) for the interest of QA for their products but maybe I am asking too much.
Where I think AMD really fell behind was they were not able to afford the kind of R&D on the manufacturing side that Intel does for each new process. AMD basically gave up and is now in the same boat as the rest of the "fabless" companies being 100% dependent on what TSMC or Global Foundries can produce. This is always going to put you at a competitive disadvantage at the very high end. While intel is working on pushing down to 22nm FINFET for the "old" architecture people in the design group are without a doubt working on 16nm and getting sample silicon at this node so they can tune their designs for what the transistors will really look like. When you go fabless you get to figure this out with poor yields while in "manufacturing" at the foundry. Maybe at 130 -65nm this wasn't such a big deal but when you need to make your design work with double or tripple patterned 193nm immersion lithography just figuring out some design rules is no simple task.
Also does anyone know if there is more than 1 vendor in the world that can make fully depleted SOI of the quality needed for 32nm - 28nm on a 300mm wafer? Last I knew this was a major reason behind Intel pushing FINFET instead of the fully depleted SOI.
Happiness is twin floppies.