According to the article: "However, phosphor powder is highly toxic and its price is expensive. As a result, Dr. Yen-Hsun Wu had the idea to discover a method that is less toxic to replace phosphor powder. This is a major motivation for him to engage in the research at the first place."

Is gold really cheaper than phosphor powder? Chemists care to chime in? Is it the powder part that increases the price?

If a single dimension changes, assuming the NAND cell structure is similar, there would be a 5x reduction in size in each of the X and Y dimensions. Therefore, you would get up to 25x more density than a current NAND. This is why process technologies roughly target the smallest drawn dimension to progressively double gate density every generation (i.e. 45nm has 2x more cells than 32nm).

The big question I have for all of these technologies is whether or not is is mass production worthy and reliable over a normal usage life.

The Vienna Symphony Library is available today and can essentially replace an orchestra to all but the most discerning of ears. Here is an example of the E.T. theme. There are a couple of parts where I can tell it's a bit artificial sounding if I really listen, but it's approaching the flawless threshold.

That said, there is a particular order of ease of simulation: percussion (including piano), strings, brass and woodwinds. The latter two are notoriously difficult to emulate because they are so closely tied to non-discrete complex forms of movement of the mouth (articulation). For example, see this demo of one of the betters saxophone emulators - still something missing even to uneducated ears, but not too bad in a mix. Strings can also be difficult to emulate, but if apps from companies like Prominy are coming out, guitars and violins, this is getting scary.

There are a couple of serious implications of this. First and foremost is what the value of a live performance is with and without musicians, which the linked article addresses. The second is decreasing numbers of people willing to learn these instruments. For a lot of folks who compose for small-budget TV and movies and can't afford musicians, it's a great way to go. Nevertheless, it's the same cautionary tale as the decline in handwriting that coincided with the rise of computers with keyboards. You can't replace handwriting in a lot of circumstances.

The MPEG-4 Part 12 standard or MP4 container is capable of nearly everything that one needs from a standards perspective to set up any kind of streaming A/V media. The metadata boxes/atoms are totally customizable and extensible even to the point of custom device application delivery. All major CODECs are supported within the container. It can be muxed in real-time (with some trickery). All one needs to do is choose the audio and video CODECs and to define the custom metadata if/when necessary, gear your tool set to your choices, and you're done. You can even do DRM and live ad splicing if you want and your system supports it. There's a reason Adobe uses it in their .f4v variant, and why online streaming content providers and even now Microsoft in Expressions are using MP4 and its variants.

MPEG TS is higher in container overhead than MP4. Vudu happens to use it in their service, but it's a cut down version and was used primarily because the set of targeted devices for playback used it(i.e. TVs and STBs). I'd never choose it if I was starting any kind of streaming media service or defining a standard. There are even plenty of tools from companies like Rhozet and Digital Rapids to be able to batch re-mux and re-encode any content from MPEG TS to MP4.

By the way, you're all over the map with your standards. ISDB-T and DVB-H are broadcast standards that encompass much more than the media container specification, like the modulation scheme and receiver-level RF tests. MPEG TS is a container format defined in MPEG-2 Part 1 and is completely agnostic to broadcast standards and that physical medium, even though it is used almost exclusively in that domain.

I totally understand the undercurrent of your comment, and I don't dispute this could be the case. From a security standpoint it may be impossible to detect hardware intervention in any ASIC they may have had, particularly since it can run in parallel with no intervention in software (or preloaded at final test or wafer test).

Huawei should have been subject to ITC embargoes years ago for their technical thievery from the Western network equipment makers. It isn't a surprise to me that this kind of backdoor would exist. People get everything they deserve for buying their equipment from a company started by a Chinese army officer and Communist Party official.

I mostly agree with you: ownership should mean total control, so I should have total freedom to do whatever I want with my physical property.

The part where I disagree with you, I nevertheless actually agree in spirit: the DMCA is bullshit. It's bullshit because it prohibits too much. IIRC, it makes tinkering with devices illegal, and that's just ridiculous.

The part where I disagree with you is that I think reasonable copyright laws are good. What if I wrote some songs or something, someone else stole the music, and became rich and famous by claiming my stuff as their original? That's just plain wrong, so I think reasonable copyright has it's place.

Unfortunately, the DMCA is not reasonable copyright.

It's not exactly great, but it's not all THAT bad. After all, it comes with a webcam and USB ports. Either one of those minor features alone add a huge boost in use value (I'd love to videochat while chilling on my couch with someone, then bring the tablet over to the kitchen and prop it up while I do dishes and keep talking! and the value of even a single USB port is pretty much self-evident!). Having both of these features for less price than an iPad is not something you can honestly ignore or dismiss.

Basically, it's 2 different products from totally different origins entering the same space: both are entering the above-smartphone-yet-under-netbook space. Both iPad and Eee are both awesome in their own way.

tldr: competition = yay!

Nice article that made me very curious about one thing: why did the Newton fail? It seems like an amazingly useful and cutting-edge device that should have been snatched up by everybody.

Maybe it was just a little bit TOO new, so didn't fit well enough into people's existing workflows?

Culture is both a cause and a consequence. Parents might magically wake up and start talking to their children about the wonders of science. Or they might not. But culture can also be another tool in the government toolkit (e.g. religion).

Your fantasy of an evil controlling nanny state versus the rebellious freedom-fighter parents is just that: a fantasy. Sometimes the government is doing something that should be done, and sometimes not; sometimes parents are doing what should be done, and sometimes not. I think everyone recognizes by now that most people don't spend time exciting their kids about science, and so the ability to reason and think clearly is declining. Hence, it's forward-thinking for someone with the power and responsibility of the President of the US to increase science and mathematics education. I don't see how any clear-thinking person could be against this.

Simplified models beget simplified thinking.

Begging your pardon for a moment, but is it not the point of university education and student teaching to provide exactly what a teacher needs to be able to do their job, and to adhere to lesson plan guidelines from state agencies and national standards? This is what I remember essentially being the case.

Again, I must reiterate: for-profit education reduces incentive to widely disseminate information. We frequently talk about open source software models being profitable not because of the content but because of the necessary services to implement it in practice. Why not the lesson plans too?

After all, if a student earns a grade for their own unique academic paper, shouldn't the teacher be required to earn their dollar for their own academic lesson plans or be penalized for it?

Reducing education to a financial transaction either needs to work both ways, or work neither way. If the teacher can buy a lesson plan and tailor it to their classroom, a student should be able to buy a paper and tailor it to their specific need too. It's an absurd example, but one that illustrates that all parties in education need to adapt to each other and not reduce things to a dollar sign and marginalize society's most important equalizer.

I meant to say that in my first paragraph that Verilog has both procedural and concurrent structures, and that its C-like syntax tends to push people to use more procedural constructs rather than concurrent which lead to gross compiler assumptions and/or non-synthesizability. In order to avoid confusion, I would therefore suggest that the strong typing in VHDL makes it easier to understand digital design in the context of an HDL. Sorry about the confusion.

You're right that Verilog has those constructs, but they're strictly used for modeling. You either won't make synthesizable code out of them, or if it handles them it's done in an implicit way that you absolutely have to know what the implications are. Again, HDLs are not programming languages in the get-to-the-chip sense, they're concurrent systems description languages. Even more reason to leave Verilog alone at the outset and learn with VHDL.

It's been about ten years since my TAs and I taught the lab section of the advanced digital logic design at my university. I agree that, generally speaking, VHDL is a better teaching language than Verilog. Part of the reason is that Verilog, being much like C, is inherently procedural. You don't want to think procedurally with digital logic except for the specific case of state machine design, and even then you have to take into account concurrency. It is this fundamental aspect of concurrency in HDLs that is key to being able to design effectively. I can define twenty clocks going into counters, just like I can wear twenty watches on my arm and have them all tell time independently and/or at different speeds. You can't really do that with procedural languages unless you're talking about thread scheduling, and then this becomes a thread scheduling exercise when you have multiple threads. Even then, you will never be able to get the speed of digital logic because you have instruction fetch, instruction decode, etc. that introduce latency that cannot be reduced even in a multi-core CPU. Not thinking procedurally will help, and the strong typing of VHDL over Verilog will help greatly in my opinion. Those Karnaugh maps you talk about are fine to learn, but HDLs use case statements in VHDL that make state machine design trivial especially when you have >8 states.

Beyond HDLs, however, are FPGAs and ASICs (and I've designed using both). Putting the differences between FPGA and ASIC aside, FPGA has some very specific ties to the vendor because of the way the FPGA is architected. Assignment of I/O, synthesis, and most of all timing constraints for guiding the "map place and route" tools for FPGAs are something you won't learn from VHDL alone (e.g. clock domain frequencies, max/min delays, input/output delays, false/multicycle paths, setup and hold times or worst-case timing paths in the design). These are essential to digital design, but not part of the HDL at all (see Synopsys SDC format for more info). In fact, shell scripts, sed/awk, Perl, TCL, Scheme and Python are also essential to know because they glue the various different tools together through scripting, processing of text files, tailing log files, and batching can be critical to being efficient. So is being thorough in understanding log file warnings and errors, timing reports. Electronic Design Automation or EDA tools also have their own idiosyncrasies, and you'll need to develop a stable "reference front-end and back-end design flow" if you haven't already. Do you use an Altera or Xilinx reference board, or an add-on PCI-based FPGA card? And how do you analyze what's coming and going at the interface? All of these questions need to be answered before you really get going on FPGAs. ASICs have an order of magnitude more complications for reasons I won't even discuss, but it just gets harder. So those state machines that you created without K maps will have synthesis pragmas that direct the compiler to create the appropriate state machine (e.g. One-hot for performance, Gray code for lower power, etc.).

Finally, there's the work world. As other posters have mentioned, North America is primarily focused on Verilog while the rest of the world is VHDL. Most synthesizable IP cores for various functions come as Verilog. So, the truth is, you should know both major HDLs, but you would be better off being proficient in Verilog in the real world for the simple reason that it is the present and future (or at least its successors, such as System Verilog, are the future) are for many reasons. Also, in the work world, it's critical to know the major EDA vendor software and to put it on your resume (i.e. Mentor Graphics, Synplicity (for FPGA), Synopsys, in roughly that order, and Cadence and Magma for ASIC) as well as all those scripting and other languages like Perl and TCL that I mentioned. Don't completely ignore VHDL, however.

As an ironic point, there are SystemC compilers for hardware that are becoming more and more crucial in large scale development for video algorithms and the like. The results tend to be difficult to formally verify (i.e. C code != Verilog out) and often inefficient or even not realizable in physical design, so you may need to go in and modify pieces heavily to be able to close timing. At your level and given the class of devices you're working on, it's quite premature to consider this, and I would strongly recommend to focus on the HDLs first. In fact, I don't even know if there's a university program for that software either.

My best advice here is to focus on learning digital design and VHDL first, then Verilog, then seeing how it applies to an FPGA kit (e.g. Altera Cyclone or maybe even MAX CPLD, or Xilinx Spartan) from a major vendor, then learn some of the other industry-standard EDA tools that work with their tools (e.g. Synplicity FPGA compiler, Mentor Modelsim waveform simulator for test benches and back-annotated (i.e. timing-aware) simulation, possibly some formal verification tools as well). This topic is way too big for even this post, and I feel like I'm swatting at a cloud of flies trying to get rid of them, but knowing FPGAs will greatly help your career since advances in process technology are making FPGAs more SoC like and cheaper all the time.