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Average Ratings 0 Ratings

Total
ease
features
design
support

No User Reviews. Be the first to provide a review:

Write a Review

Description

Ansys VeloceRF accelerates the design process by significantly cutting down the time required to synthesize and model intricate spiral devices and transmission lines. Compiling the geometry of inductors or transformers takes just a matter of seconds, while modeling and analyzing them can be completed in just a few minutes. This software seamlessly integrates with top EDA platforms, creating layouts that are ready for tape-out. With Ansys VeloceRF, users can synthesize devices that tightly pack multiple components and lines, resulting in a more efficient silicon floorplan. Furthermore, analyzing the coupling effects among various inductive devices prior to detailed layout can decrease the overall design size and potentially eliminate the need for guard rings. The dimensions of inductors, along with crosstalk between them, can significantly influence the size of the die. Ansys VeloceRF assists in designing smaller devices by applying optimization criteria and geometry constraints, leading to enhanced performance. Additionally, it assesses the coupling between any number of inductors, optimizing both silicon area and inductor performance within the circuit context, ultimately contributing to a more efficient design process. By streamlining these aspects, Ansys VeloceRF empowers engineers to achieve their design goals more effectively.

Description

With the rapid advancements in microprocessor technology, application developers increasingly turn to Green Hills Compilers to harness the complete capabilities of hardware, ensuring optimal performance and functional safety in their upcoming applications. The compilers are equipped with cutting-edge optimizations designed to enhance program performance while adhering to stringent size limitations. A notable feature, CodeFactor™, enhances execution speed and minimizes code size by eliminating redundant code segments through techniques like subroutine calls and tail merging. Similarly, static basing optimizes performance and reduces size by organizing data items, which cuts down on the number of load address operations needed. Each optimization, whether a novel creation or an established industry standard, undergoes a thorough implementation process. For over thirty years, our commitment to engineering excellence has driven us to meticulously research and rigorously test each optimization against a wide array of benchmarks to ensure the highest quality. This dedication to innovation guarantees that developers can confidently rely on our tools to elevate their applications.

API Access

Has API No 

API Access

Has API Yes 

Screenshots View All

Screenshots View All

Integrations

INTEGRITY RTOS No 
MULTI IDE No 
RTX No 

Integrations

INTEGRITY RTOS Yes 
MULTI IDE Yes 
RTX Yes 

Pricing Details

No price information available.
Free Trial No 
Free Version No 

Pricing Details

No price information available.
Free Trial No 
Free Version No 

Deployment

Web-Based Yes 
On-Premises No 
iPhone App No 
iPad App No 
Android App No 
Windows No 
Mac No 
Linux No 
Chromebook No 

Deployment

Web-Based Yes 
On-Premises No 
iPhone App No 
iPad App No 
Android App No 
Windows Yes 
Mac No 
Linux Yes 
Chromebook No 

Customer Support

Business Hours Yes 
Live Rep (24/7) Yes 
Online Support Yes 

Customer Support

Business Hours Yes 
Live Rep (24/7) No 
Online Support Yes 

Types of Training

Training Docs Yes 
Webinars Yes 
Live Training (Online) Yes 
In Person No 

Types of Training

Training Docs Yes 
Webinars No 
Live Training (Online) No 
In Person Yes 

Vendor Details

Company Name

Ansys

Founded

1970

Country

United States

Website

www.ansys.com/products/semiconductors/ansys-velocerf

Vendor Details

Company Name

Green Hills Software

Founded

1982

Country

United States

Website

www.ghs.com/products/compiler.html

Product Features

PCB Design

3D Visualization No 
Autorouting No 
Collaboration Tools No 
Component Library No 
Design Rule Check No 
Differential Pair Routing No 
Schematic Editor No 

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