Flash Density Increasing w/25nm Triple Level Cells

AaronLS writes: StorageReview.com has a story indicating Intel and Micron planning production this year for Triple Level Cell flash on 25nm Lithography. This means that 3 bits instead of 2 can be stored in each cell, and the smaller 25nm Lithography generally allows more cells to be fit in the same area.
  This combination should provide a considerable improvement to the density, and hopefully cost, of flash based storage. Read more at StorageReview.com: http://www.storagereview.com/intel_and_micron_announce_25nm_triple_level_cell_nand