There's no comparison. All science fiction is a mirror on the time it was written. Imagine writing a SciFi novel in 1890 where the characters worry about what cell phone plan to use and if they should have cable or DSL for twitter and hulu. No one would understand it. So all these future people (and blue aliens on Avatar) are really humans of their author's time. Star Trek has the disadvantage of spanning 30+ years. So Kirk was the prototypical 60's guy. Kick a**, take names, and get it done. I realized this on one of the very early STNG episodes. I think it is the one where they meet the Ferengi (or however you spell it) the first time. Situation: There is an unknown enemy craft in a hostile position hovering off the starboard bow. What does Picard do? What any 90's guy would do. He calls a meeting. No kidding. "Everyone to the reaaadddy room" (hard to type an accent). The second string takes up the bridge and they hold and honest to goodness corporate style meeting that Dilbert would have been at home in. Of course, I'm a Kirk fan but I'm also a child of the 60s and don't have much patience for meetings (current day job notwithstanding).

My mom never says WTF. Well. Almost never.

Given this was in the embedded portion of Dr. Dobb's I don't think anyone in that audience cares about x86 compatibility. PICs, AVRs, and ARMs won't run a line of x86 code but are quite popular. In the FPGA space, ARM and PPC are both well represented. Ditto for speed. A 32 bit CPU at 10MIPs is handling 40 megabytes per second (and that's not the maximum speed for One-Der). A PIC running at 5MIPS (20MHz clock) is handling 5 megabytes per second.
Even in the "PC" space. I have an Arm-based processor that runs Linux, gcc, and just about any piece of code I want. If we could ever get a mass market CPU that DIDN'T have to maintain a 23 year old instruction set so it can boot MSDOS we could really get some inexpensive horsepower.
As for the original comment, lose on performance is unsubstantiated. With the correct functional units for a particular task, a processor like this can blow the doors off of a generic CPU. Code density. Sure. But its an engineering trade. Do I make my datapath more complex or do I spend on memory? There's not one right answer for that (or most design trades, for that matter). In some applications, I'd rather simplify my datapath and add custom instructions with ease and buying a few memory chips isn't killing me. In some cases, though, I agree you'd want to trade the other way and work harder to conserve memory. Of course, there's opcode compression (a la VLSI) etc.
Each CPU I've ever designed has been different and that's because they were built for different purposes. The idea that one CPU architecture, or one programming language, or one brand of computer, or one operating system is The One True Way is fanboy religion and I've never really got that. Well, other than emacs vs vi. That's a worthy argument I can be baited into.

Here's what I do. I put a copy of some sort of VNC on THEIR machine. I might even walk them through doing it themselves on the phone if I must. But you are right, it is pain to get them to find their IP, open up ports, etc. So. What you do is you open up port 5500 and get yourself a dynamic IP address (xxxx.dyndns.org or whatever). Then you run vncviewer -listen on your machine (assuming Linux). Then when they run to connect their VNC server to xxxx.dyndns.org you are in. How they do that depends on what VNC server you put on their machine. Once you are in you make a shortcut on their desktop that says something like "Show my Screen to the Genius" and then you are set for life as long as they are able to boot to the OS and get to the Internet. Simple and it works.

http://www.youtube.com/watch?v=YYdpRV29_Y8 - Actual 2nd gen hardware
http://www.youtube.com/watch?v=KnQGcoe6oGg - Software simulator

Of course it has multiple operations. But in fact it has a single instruction. The CPU's control unit treats every instruction the same. Now if you want to nit pick, yes the immediate load format makes it really a 2 or 3 instruction machine. But your argument is confusing operation with instruction.
Think of an analogy of a C program. If I write:
void foo(int cmd) {
switch (cmd) {
case 0: // do zero stuff
break;
. . .
Do I have one subroutine or many? I have one subroutine. The fact that it carries out multiple operations is not relevant to the count of the subroutines even though I could certainly write "n" subroutines foo0, foo1, foo2, etc.

Apparently RMS and Linus are both too violent to get the peace award: http://xkcd.com/225/

Well I don't think switching between ARM and Thumb mode counts ad variable size instructions in the purest sense. However, the newer ARMs have Thumb-2 which has nearly the entire ARM instruction set (and some new things) in Thumb mode and has some 32 bit instructions along with the traditional 16 bit Thumb instruction. Not only do some of the newer ARMs support this, some like the Cortex-M3 apparently ONLY support this and ARM clearly wants this to be the "default" mode going forward. My only complaint is they had ARM and THUMB. Then they went to THUMB2. I would have named it MIDDLE-FINGER.

I think the fact that extensions appear on the Mozilla add on site could give some users the impression that they are "trusted" in some way. By default, FF won't install except from there (and maybe one or two other sites). But as far as I know, there's no real check. I mean I'm sure if you put up a extension that wiped your hard drive, enough people would complain and comment that it would get yanked. But something more subtle, maybe not.

But that does in fact reduce complexity when you go to add new "instructions". Suppose you want to add a multiplier. You simply build a module that does multiply, verify it, and then hang it off the bus. Same goes for if you want, say, a second stack (for the Forth compiler, for example). You just make a new instance of the stack FU.

It is very difficult to add instructions to microblaze. Beyond that, it would be even harder to have a compiler reconfigure the ISA of microblaze on the fly.

Actually, there is a newer version that handles interrupts (required a very small set of changes in the core and all the interrupt hardware is in the FIO block except debugging interrupts which are in a new FDEBUG block). Saving the processor state is no worse than saving the things you use on the stack just like any other processor. There's more on this newer version at: http://www.awce.com/classroom/course/view.php?id=11