SystemC Integrations

Coco®, a tool for multi-language code coverage, is available. Automated source code instrumentation can be used to measure test coverage for statements, branches, and conditions. When a test suite is run against an instrumented application, data can be collected that can be later analyzed. This analysis can be used for understanding how much of the source code was touched by tests, which additional test suites need to be written, and how the test coverage has changed over time. Identify dead or untested code, redundant tests, and untested code. Identify the impact of a patch and code coverage. Coco supports branch coverage, statement coverage, MC/DC, and other levels. Linux, Windows, RTOS, and other platforms. GCC, Visual Studio and embedded compilers are all available. You can choose from text, HTML, XML and Cobertura report formats. Coco can also integrate with other build, test, and CI frameworks such as JUnit Jenkins, SonarQube, and SonarQube.

Linux, Windows, RTOS, and other platforms. Using Visual Studio, embedded compilers, and more. Multiple execution reports can be combined to provide advanced analysis and other outstanding features. Coco's Function Profiler allows you to evaluate and optimize code performance.

ModelSim simulates RTL and gate-level code. This increases design quality and productivity through platform-independent compilation. The single kernel simulator technology allows transparent mixing of VHDL with Verilog. ModelSim is a cost-effective HDL simulation that offers an unprecedented level in verification capabilities. It is ideal for verifying small and medium-sized FPGAs, especially those with complex, mission critical functionality. ModelSim's advanced coverage capabilities are valuable metrics for systematic testing. ModelSim is easy to use, which lowers the barrier to leveraging verification resources. All coverage data is stored in UCDB, a highly efficient database. Coverage results are available interactively, after simulation, or following a merging of multiple simulation runs. FPGA designers can debug their designs using an easy-to-use, unified environment.