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Average Ratings 0 Ratings

Total
ease
features
design
support

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Write a Review

Description

ModelSim effectively simulates behavioral, RTL, and gate-level code, enhancing both design quality and debugging productivity through its platform-independent compilation. Its unique single kernel simulator technology allows for the seamless integration of VHDL and Verilog within a single design framework. This HDL simulator offers an unparalleled range of verification features at a competitive price, making it particularly suitable for the verification of small to medium-sized FPGA designs, especially those that are complex and mission-critical. ModelSimโ€™s sophisticated code coverage tools yield essential metrics that aid in systematic verification processes. Additionally, its user-friendly design minimizes the obstacles to utilizing verification resources efficiently. All coverage data is securely stored in the highly efficient UCDB database, providing flexibility in how results can be accessed. Coverage outcomes can be analyzed interactively, either during or after simulation, including after merging results from multiple simulation sessions. This unified and easy-to-navigate environment equips FPGA designers with the necessary advanced tools for effective debugging and refinement of their projects.

Description

Identify issues at the earliest stages and enhance your design's reliability by implementing formal checks and properties. Integrate formal methods early in the design phase whenever they align with your application's needs. Utilize formal cover traces to deepen your understanding of the design and address challenging questions regarding the design being evaluated. Leverage formal safety properties to create more concise and meaningful traces than those generated through simulation. Use formal proofs to validate your design's accuracy, apply mutation coverage to bolster your confidence in simulation-based verification efforts, and streamline the test case creation process by utilizing guidance from formal cover traces. Engage in both unbounded and bounded verification of safety properties while conducting reachability checks and detecting bounds for cover properties. This comprehensive approach not only ensures design correctness but also fosters a more efficient workflow throughout the development process.

API Access

Has API

API Access

Has API

Screenshots View All

Screenshots View All

Integrations

Siemens Precision
SystemC
Xilinx

Integrations

Siemens Precision
SystemC
Xilinx

Pricing Details

No price information available.
Free Trial
Free Version

Pricing Details

No price information available.
Free Trial
Free Version

Deployment

Web-Based
On-Premises
iPhone App
iPad App
Android App
Windows
Mac
Linux
Chromebook

Deployment

Web-Based
On-Premises
iPhone App
iPad App
Android App
Windows
Mac
Linux
Chromebook

Customer Support

Business Hours
Live Rep (24/7)
Online Support

Customer Support

Business Hours
Live Rep (24/7)
Online Support

Types of Training

Training Docs
Webinars
Live Training (Online)
In Person

Types of Training

Training Docs
Webinars
Live Training (Online)
In Person

Vendor Details

Company Name

Siemens

Country

United States

Website

eda.sw.siemens.com/en-US/ic/modelsim/

Vendor Details

Company Name

Symbiotic EDA

Founded

2018

Country

Austria

Website

www.symbioticeda.com/seda-suite

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