This is what annoys me most about modeling hardware in VHDL, verilog, etc. versus programming software.
With software, the goal is to fix any warning messages (even with -Wall), to the point that many programming standards require -Werror as well. The warnings are generally important to follow and are generally heeded.
With hardware, synthesizing a design produces hundreds of warnings even with simple designs -- many of which warn about common, intended behavior. Maybe I just used crappy tools? Either way, the warnings were ignored simply because they didn't seem to be important.
The lesson: don't overload the user with warnings, but use them selectively and usefully.