There are two better examples in the engineering world: FPGA design and 3D CAD.
The FPGA design process has some parts that are embarrassingly parallel - compiling many source modules into RTL for example. There are also some phases that must be done sequentially, like place-and-route. Medium-sized FPGA designs (something that takes ~70% of an Artix-7 200k gate device) take about 30-40 minutes on my I9-9880H. Larger designs, like something targeting the multi-million gate Virtex and UltraScale chips (and others from Intel/Altera or Lattice) take hours to synthesize. This gets worse when the design uses more of the FPGA fabric, or when there are tight timing requirements. Parts of the process are iterative, with a dependency on data from prior iterations, which prevents parallel processing.
Similarly, CAD software like SolidWorks has to process the feature tree sequentially, because each feature may be dependent on any or all of the features that came before. There's no good way to tell with absolute certainty whether there might be a dependency, and even if there were, the dependency checks would have to be re-done after every change, no matter how trivial. This is because something simple, like changing a fillet radius, could cause a dependency for a seemingly unrelated feature somewhere down the line, like a hole on one of the surfaces that the fillet touches, which would prevent firing off a separate thread to e.g. work out the geometry of that hole.
These examples are the FPGA and CAD equivalents of waiting for code to compile. That's relevant because the engineer is typically waiting for these processes to complete, so overall processing time (ie, latency) is important. Maximum single-core speed makes a big difference because of the sequential processing, maximum multi-core speed also makes a big difference because of the parallelizable parts.
There's no single answer like you're saying, it's a balancing act depending on the workload.