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Comment Re:Yeah, um, not so much (Score 0) 819

Gosh, I'd love to find the link and read the whole context of your Daniel Webster quote. I tried to googled it, and my meager search skills were unable to locate the source.

And, given the stuff Webster has written elsewhere about the public health approach, see http://annals.org/article.aspx... this quote doesn't really sound like Webster...

Comment wonder if it's a big LITTLE architecture? (Score 1) 136

From what I've read about AMD's Zen architecture, they've dispensed with the "two single threaded cores per module" architecture and now have SMT allowing two threads in each core according to this, much like "hyper threading" on Intel chips.

If that's the case, and we can expect a 32 core chip to execute 64 threads, then that's an awful lot of threads to keep supplied with data and instructions. In comparison, the biggest Intel Xeon I know about, the E5-2699 v3 has 18 cores, 36 threads, 45MB of last level cache, and 4 memory channels (68GB/sec to RAM). Intel sticks pretty close to that 1.25MB cache per core in their big Xeons. So if you adhered to Intel's apparent rules, a 32 core 64 thread chip would need 80MB of LLC and maybe 6 memory channels. Anandtech estimates 5.7 billion transistors for the big Xeon. Scaling the Intel design from 18 to 32 cores would require over 10 billion transistors! That number leads me to believe that an SMT 32 core 64 thread chip built with 2016 technology would not be practical.

What might be practical is a chip with some "heavy" cores optimized for balls-to-the-wall floating point execution, and other "lighter" cores for lower power integer tasks. This has been done in "octocore" mobile phone chips and called a big LITTLE architecture. The idea is that the OS and various decoding and checksumming tasks can stay resident on the low power light cores, while the heavy cores do things like game physics and photo noise reduction. Because the multiprocessing is not symmetric, the OS kernel needs special rules to assign tasks to cores. Which leads me to wonder if AMD has something like big LITTLE up its sleeve for 32 core Zens.

Comment Re:Dumbing Down (Score 5, Informative) 54

"it could begin the next instruction while still computing the current one, as long as the current one wasn't required by the next " Doesn't this go without saying?

Back in the day, pipelining - issuing, say, a new multiply instruction every clock, even though several earlier multiplies were still working their way thru the pipeline - was too expensive for most architectures. An instruction might take multiple clock cycles to execute, but in most architectures the multi-clock instruction would tie up the functional unit until the computation was done - you might be able to issue a new multiply every 10 clocks or something. Pipelining takes more gates and more design because you don't want one slow stage to determine the clock rate of the whole design.

Which leads us to the early RISC computers, I can recall an early Sun SPARC architecture that lacked a hardware integer multiply instruction. The idea at the time was every instruction should take one clock, and any instruction that demanded too long a clock should be unrolled in software. So this version of SPARC used shifts and adds to do a multiply. At the time, that was a pure RISC design. One of the key insights in RISC, still useful today, is to separate main memory access from other computations.

The CPU design course I took in the late 80's said Seymour Cray invented that idea of separating loads and stores from computation, because even then, even with static RAM as main memory, accessing main memory was slower than accessing registers. So by separating loading from RAM into registers and storing from registers into RAM, the compiler could pre-schedule loads and stores such that they would not stall functional units. Cray also invented pipelining, another key feature in most modern CPUs (I'm not sure when ARM adopted pipelining, but i'm pretty sure it's in some ARM architectures have it now). Of course Cray had vector registers and the consequent vector SIMD hardware.

I don't think Cray invented out of order execution, but I don't think he needed it; in Cray architectures, it would be the compiler's job to order instructions to prevent stalls. In CISC architectures, OOO is mostly a trick for preventing stalls without the compiler needing to worry about it (also, with many models and versions of the Intel instruction architecture out there, it would be painful to have to compile differently for each and every model). So, for example, the load part of an instruction could be scheduled early enough that the data would be in a register by the time the rest of the instruction needed it.

Anyway, the upshot is modern CPU designs have a bigger debt to Cray than to any other single design.

Comment Re:What happened = gambling + sports (Score 2) 95

Any time gambling gets mixed with sports you have a mechanism where cheating can get you money. Whether it's the 1919 Chicago "Black Sox" or one of these point shavers gambling always has the potential to lead to sports cheating.

... Which makes you wonder why the US professional leagues have invested their own money in fantasy sports gambling sites.

Comment How about if we OWN our personal information? (Score 5, Interesting) 79

Imagine if we owned our personal information as a form of intellectual property? Big corporations have gotten pretty good at protecting their intellectual property rights. Maybe it's time for us ordinary folks to own our personal information. Then we could license it to companies for particular uses, but they wouldn't have the right to sell it without our permission.

Comment Re:Does not crash Chrome on my Win7 laptop (Score 1) 205

It does not crash the copy of Chrome running on my Win7 machine. I let the machine automatically update when it feels like it; the machine is currently running Chrome 45.0.2454.93

When I paste http: //a/%%30%30 into the address bar, I seem to get a web search for 30 30, with the first two hits being .30-30 Winchester - Wikipedia & 30/30 Poetry. I get the exact same behavior pasting into the search box. So it seems the current default behavior is to treat a malformed URL as a text search.

P.S. This meme should be a bonanza for the good folks at 30/30 poetry!

Comment Re:Don't take yours in. (Score 1) 411

Diesels are better at CO and unburnt hydrocarbons, because they always take in a full charge of air, no matter how small an amount of fuel is being injected (therefore combustion is more complete). They may be marginally better at CO2, but that is mostly because they tend to be under powered compared to "performance cars".

Comment Re:Same reason we're looking for earth-like life (Score 1) 275

Radio is very noisy. Why would any advanced civilization think that it would be a great way to communicate over long distances?

Because microwaves near the 21cm band pass through dust clouds that would block visible light and various other frequency bands, so its good for really long distance communication. Hydrogen 21cm detectors are also a good way to measure the large scale structure of the universe. See The Watering Hole.

Comment Maybe it's time to tax intellectual property (Score 5, Interesting) 128

OK, I get it, intellectual property is a real thing and needs a certain amount of protection. But you know what? Protecting property costs money! I own a condo and I pay taxes on it - something like 2% of the property value per year! Obviously the tax rates for IP need to be set at a reasonable level, but if a company is claiming x billion dollars of IP, perhaps they ought to pay a tax of a few hundred thousand for property protection. And if they lapse in their tax payments, perhaps their ownership rights lapse too, just as the city or state would take over my property if I stopped paying taxes.

Comment Re:That's pretty surprising for 2015 Android IMO (Score 1) 287

Android supports RDNSS for IPv6, but not DHCP for IPv6. Basically, there is no need for DHCP in IPv6. There is no need for an IPv6 address to be dynamic. Your carrier has multiple ways to supply one or more global IPv6 addresses to your mobile device, and to renumber the devices under its control at any time. Since your carrier is responsible for routing the IPv6 packets from your mobile device, it's up to your carrier to assign IPv6 addresses. For use on a local network, your device can also use IPv6 stateless auto configuration. Also, none of these options exclude any others: IPv6 assumes devices will have multiple addresses at the same time. Finally, IPv4 and IPv6 are not mutually exclusive. If you are behind a firewall, using addresses like 10.x.y.z or l192.168.x.y, then your device is capable of using IPv4 and IPv6 simultaneously.

On my android 4.1 phone, connected via Verizon, I can see both an IPv4 address and an IPv6 address. On my phone, tap Settings, scroll to the bottom, tap About phone, then tap Status, and you'll see a field of two IP addresses. With wifi turned on, I have a 192.168.x.y address on my home wifi network. If I turn wifi off, I get an address that begins 100.71, presumably assigned by Verizon and globally routable. With or without wifi, I have a second address with 8 fields, much longer, beginning 2600:1000. That's clearly an IPv6 address assigned by Verizon. Whether or not Verizon will route my IPv6 packets is another question.

Comment Re:DUHHHHH (Score 5, Interesting) 124

Whoever hacked Kaspersky was probably hunting moles. From the outside, it looks as if Kaspersky has been positively brilliant, revealing state level actors, cracking stuxnet, duqu, & duqu2. But what if some other state level actor had been feeding Kaspersky? What if spies, not security researchers, told Kaspersky where to look? It would be worth a lot for the authors of stuxnet etc to be able to confirm or deny that Kaspersky worked without help. That's the best reason I can see for hacking into Kaspersky.

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