SRAM uses circuits that resemble a flip-flop
, e.g. a latch, which would be what GPP was referring to. You are correct though that SRAM preserves state for some time after removing power, again especially at colder temperatures. However, I don't imagine it will be too much trouble, as getting a CPU to dump latent data from its cache after a power cycle is probably quite difficult -- it's small enough and fast enough that I would be surprised if the CPU didn't just zero the entire thing on boot. Certainly you wouldn't be able to get it back out the same way it went in as retrieving cache lines that are not really there would be a bug.