Comment Re: Exciting (Score 3, Informative) 74
What? No. I don't know where you got that from but FPGA was NOT what RISC-V was invented for!
"RISC-V was started with a goal to make a practical ISA that was open-sourced, usable academically and in any hardware or software design without royalties." (Wikipedia).
The simplicity of the ISA goes back to the original goal of RISC: stop wasting silicon real estate on circuits to support thousands of legacy (what Linus would call "magical) opcodes that you have to support in every future version of your ISA. Swaths of the circuits in an x86 chip are more or less never used because compilers over time ditch the garbage pile that is Intel's instructions-of-the-week. ARM has the same problem, even though they evolved from a RISC design. My favorite example is ARM *still* has a Java acceleration opcode left over from the Blackberry days. Now, it just feedback into their main execution pipe, but they can never get rid of the opcode or implementing the circuitry to support it.
Modern x86 chips are basically RISC on the backend, with a bunch of circuitry on the front end to decode those x86 ops into
one or more RISC micro-ops. You're basically wasting silicon to support x86.