Comment Re:not really (Score 1) 256
The article is talking about enterprise-grade SSDs using data from 2012. As for the performance difference, it seems to be mainly due to the difference between SLC, MLC, and TLC. From page 4:
Even if economic forces are favorable to continuing price reductions of SSDs and NAND flash, a 2012 study by Microsoft Research (PDF) has found that a dilemma arises when trying to increase density and reduce cost of SSDs. The study looked at 45 flash chips from six different manufacturers and found that, as density increases, bit error rate (BER) and performance decrease. This is because the number of ranges of electrical charges necessary to store data on a single cell increase as densities increase.
The researchers found that, as feature size decreases (increasing density), bit error rates increase. While the SLC and MLC chips with cells that had feature sizes of between 80 and 60 nanometers (nm) usually had BERs of 1e-08, those with feature sizes of 40 nm had BERs at or below 1e-07, and the TLC chips with feature sizes of 20 nm had BERs of, at best, 1e-03.
In addition, researchers also found that increasing density also increases read and write latencies. NAND chips with feature sizes above 64nm had read latencies of 20us or less and write latencies of 0.5ms or less, while those with feature sizes of 32nm or less had read latencies between 20us and 60us and write latencies between 0.5ms and 2.5ms.
This leaves SSD and NAND manufacturers with a choice among density, cost, reliability, and performance. In any scenario, at least one of these four must be sacrificed to improve the others. This means that, even if SSDs can achieve cost parity with HDDs, it will be at the expense of reliability, density or performance. In fact, as discussed above, enterprise-grade SSDs already sacrifice write performance, cost and even density to address the threat of reduced reliability and data integrity and have built non-2.5” form factor configurations and added special coding or technologies to meet reliability and performance demands, resulting in more costly products.
[emphasis mine]
More bits per cell requires more precise current sensing, which slows down reads and writes. I suspect parasitic capacitance due to the physical size of the array is also a factor. Performance is also affected by the controller, which may mask some of the bit-level performance differences.