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Comment Re:Fix? (Score 1) 140

Timing errors are always the hardest things to track down. Fortunately we are talking about a fully digital ASIC with one clock domain, except for the memory controller, and some other things I might have ignored. I recently finished a project where we converted a FPGA to an ASIC that had more than 180 clock domains. That, my friend, was hard.

The logic bugs are mostly tracked down in simulation, and on the FPGA prototypes. Remember that the openRISC CPU has been available for some time already, runs Linux 2.6.38 fine and is being used in the industry. The RTL is mostly done except for ASICification of some parts.

The fear of suppliers running out of MCUs is real, I can tell you. Reverse-engineering of chips, and reimplementation in FPGA happens all the time in the industry. It is expensive and time-consuming, so having the source code and constraints around is a big help.

Comment Re:OK, I'll Say It (Score 1) 140

If your order volume is small, the fixed costs will eat you alive.

...which is why opencores is asking for donations

There is a block level view of what's going in, which is mostly off-the-shelf OpenCores cores, but there are no detailed plans about how this is going to be translated into an actual ASIC design.

1. Push ASIC button

2. Profit

Just kidding :) The CPU itself has been turned into ASICs before, so most of the code is in a good shape. The rest is implementation details and will probably be worked out when the ASIC vendor is chosen.

There are only plans for making a FPGA based development platform.

Don't get me wrong, a FPGA platform is a good thing to do. A project like this won't have the resources to do very much design validation through simulation (which requires lots of people writing tests and running sims, i.e. real money), so FPGA based prototyping and validation is even more important than it is for conventional "closed source" ASIC projects. However, there is no plan given for how they're going to take their working FPGA design and turn it into an ASIC design.

Verification is always the largest issue when you are building complex systems. One of the benefits of open source however, is that someone might have done it before you. In the case of the OpenRISC CPU, the 80000 (correct me if I'm wrong) regression tests of GCC is being used as one source of verification stimuli. Keep in mind also that the design isn't being created from scratch. The core is about ten years old

It's somewhat revealing that they're using a single small Altera Cyclone IV FPGA (under $60 qty 1 through Digikey). If you don't understand the significance, this means their design is tiny and trivial and low tech by current standards.

This isn't an effort to create the next-generation-273-bit-mega-hyper-threaded-with-DDR-5-and-379-core-subpixel-shader-gpgpu on crack. It's a fairly standard 32 bit RISC SoC, with the main difference that the RTL code is open source, and that the ASIC will be sold at a low cost even in low quantities. Think of how popular the Arduino platform is for example. It has some extra street cred, because the layout is open source. Now this is taken one step further, by using a LGPL:d CPU and peripherals. The quaking-in-their-boots part sounds a bit exaggerated, but still, it is primarily because this hasn't been done before. And if it turns out good, there is an ASIC proven SoC that can be modified and recreated by anyone that doesn't want to pay an ARM or a MIPS license for a 32-bit RISC system. Also, by using a fairly cheap FPGA, a reference board with either the ASIC or the FPGA can be sold at a reasonable cost.

Comment Re:Free at last (Score 1) 140

Sparc has been open since start when it comes to specifications, and the Verilog code has been open for many years.

Yes, that is true, but this is an attempt to produce a complete open source SoC as an ASIC, not just the CPU.

Opencores is a private held swedish company today making money by ads and consultants, it is not a .org company like opencores once was and this was a great ad!!

I think you confuse things here. The opencores servers are paid for by ORSoC. Opencores itself is the same as it always has been. Kind of like a sourceforge for HDL code. The ASIC project is partially funded by ORSoC as you can see on the donations page.

You cant make chips like that

I don't understand what you mean by that? This is exactly what opencores is trying to do

Comment Re:MIPS (Score 2) 140

Not sure about MIPS, but ARM is quick to act if someone puts out ARM clones, and I guess the same principle would apply to MIPS clones, as they both are licensable. The difference is that the R3000 is from 1988 (according to wikipedia), which probably makes it less interesting

Comment Re:Fix? (Score 2) 140

Yes you can monitor every clock cycle. In a simulator, that is. Also, I'm well aware that most vendors ship good documentation, and of course, opencores can probably not afford to ship replacement chips if a bug is found after the chips have been manufactured. However, it's a known fact that we have problems with undocumented hardware on Linux. Being able to fully analyze not just the CPU, but also ethernet, PCI, USB and other peripherals should be a welcome addition for all those that are writing drivers or debugging a strange hardware behaviour. I have no comments on your last two sentences

Comment Re:Nice idea, but many pitfalls... (Score 2) 140

I understand your critisism, and I also would like to see a more detailed plan. Since this is a pilot project, some things will have to be worked out during the planning phase.

1. If this doesn't catch on and people want it to continue, this could be a significant ongoing cost for running this project above and beyond allocating what people might think are one-time NRE charges. None of this appears to be detailed enough on that site so I'm not sure how far they've thought through this. Who are the target vendors, and have they tendered bids? Costs vary greatly, and I'm not at all ready to throw money when there appears not to be an "open source" plan with sufficient detail to make this real, nor with open listing of the credentials of the individuals involved. If you're gathering up to $250k for a project and you want my money, I had damned well better know that you're able to execute and that you have a real plan and definitely not just an FAQ.

As it is stated in the FAQ, the more money donated, the smaller process opencores can afford. That will also decide the possible ASIC vendors that can be used. I'm a bit curious about what other costs than the NRE that you are thinking of

2. How did they define the product? Is it based on market needs? If so, what markets and where is the information on said markets? If it's for hobbyists, I get that, but did anyone do even a rudimentary survey to say how many timers or UARTs might be necessary, whether they should embed an MMU so you can run a more advanced OS, or what the max CPU clock speed should be? If *I* am going to put my money in it, then why not ask *me* what I want? And yeah, I know I can contribute, but how have all of those contributions been managed, organized and synthesized into what is being built AND make it sufficiently relevant for enough time that this would be worth doing before technology moves on? I don't see a single place for that around their site.

The OpenRISC has been used in many projects before. The IP cores that are going into the ASIC should cover most basic needs. There is also a PCI bus included to cover some additional uses. A MMU will most certainly be included, since it is targeted towards running standard Linux. The CPU speed will be limited by the process, and the current design. Still, I agree that there should be a place for these kinds of discussions. I'm guessing there will be one. For now, slashdot will have to do :)

3. Frankly, why bother when there are many other vendors such as Microchip who offer 32-bit micros with fully-documented architectures and better capabilities that you can run Linux on? I know, I know, this is what open source is about, but we're not just talking about someone's spare time on a machine they do other things with; this is a real product with real implications. I seriously don't buy how they're going to change the industry since the successful players in the industry guarantee supply to their customers.

I think there are a lot of use cases for this. You can buy these cheap ASICs and build a system. If you need to hardware accelerate something, then you can replace the ASIC with a FPGA and extend the design. Come to think of it, it seems kind of backwards to prototype on an ASIC and then implement it in a FPGA :)

I know I'm going to get flamed and down-voted for this post, but the open source hardware world is much tougher than the software world, and ASIC designs are steadily dropping because ASSPs are taking their place. I think people's efforts need to be focused on software, and this is coming from a guy who's been on Slashdot more than a decade with a hardware background (and hence my name) and has switched to the software and systems world...

I really hope that you are wrong here. Open source efforts should be able to handle as much criticism as other projects. Regarding your other point, what I see is that the borders between hardware and software are changing. Things that used to be done in ASIC is now done in software and the other way round. There are also many cool ideas how to decide what is going into hardware and software at compile time.

Comment Re:Fix? (Score 2) 140

But looking at the code and create workarounds that you know are working is a big step from guessing. Also, it theoretically enables you to optimize things, when you can monitor every register and clock cycle. Don't think that is very usable in reality though, but who knows. You don't need to donate $25 by the way. One dollar is fine

Comment Re:HDCaml (Score 3, Informative) 140

Haven't heard of HDCaml before, but the idea of inventing a nicer languange than Verilog and VHDL lives on. System Verilog adds a lot of syntactic sugar and new functionality, and there is a cool project called MyHDL that uses Python. System Verilog is gaining popularity in the industry, but unfortunately there aren't any open source tools to work with it yet. The commercial ones don't seem to implement the full language either. A bit like the HTML5 situation. We could really need something though. Even after having spent nearly ten yers doing hardware design, I find the two main languages horrible to work with.

Comment Re:OK, I'll Say It (Score 2) 140

No one has chip fabs in their basement. So someone will have to pay big money to make the masks and tape-out and test the hardware.

This is why opencores is asking for donations

Unless some major vendor picks up the design and mass produces it lots of 100s of thousands, the price per CPU is going to be stupidly more expensive than an off-the-shelf CPU/motherboard or embedded system.

Not necessarily. Of course, the more chips that are produced, the cheaper they get, but this is also a non-profit effort, so if you are looking to buy low quantities, it might be cheaper than commercial offerings

Comment Re:Price? (Score 1) 140

The price will probably depend a lot on the fab method, but the goal is to make it cheap and available. The main difference between this and beagleboard/arduino/freerunner is that they are all closed source ASICs. This is both a philosophical difference (Yeah! It's open source) and a practical (I wonder why the CPU is acting strangely, Oh well, I just have to look at the source code)

Comment Re:A little outdated don't you think (Score 1) 140

The OpenRISC spec supports 64-bit, but the current implementation is 32 bit. I agree with the GPU part. There is a cool project that has built a FPGA-based graphics card http://wiki.opengraphics.org/ . One problem with the open source hardware community is that it is a bit fragmented. Would be awesome to combine a lot of the efforts.

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