Define "free". We have these things here in Germany called "lots of taxes".

Besides, I know a guy who worked for Deutsche Bahn and he was going on about a burocratic nightmare it was.

Why? I Was working on a control GUI for an embedded system running. DOS THIS VERY MORNING. It uses a Web GUI to control a set of Plasma Arc lamps that can explode or burn out so it is somewhat safety-critical. Program uses a telnet like protocol to switch the lamps on and off.

The irritating thing is that DOS's added on TCP stack is stupid, it cannot time-out a connection. So if your program crashes? Tough, reboot. If you pull the network cable? Tough. Reboot. If you test yourprogram and just quite it? Tough. Reboot. And every time you rebot, due to a safety feature those lamps go into an auto-cooling mode for 15 minutes.

That system has been running since 2007 and it was written by a crazy hermit living in a hut in the Alps who only worked from 22:00 to 06:00 (I know, I had to call him once about something) It is very reliable though, it has been working for 15 years!

No archaeology here, DOS is alive and well.

Proxmox the greatest invention since sliced bread.

We have a local hybrid/cloud provider here where you can rent servers or cloud instances with specific servers. Their support is very good as is the reliability. What is flaky is the ProxMox install image. Always in Beta. Fair enough, ProxMox is so good it would be competition for them.

Neither was MacOS. macOS X came out after the single event loop of the old OS became a serious disadvantage for the same reason

> RISC-V will do to the CPU market what Linux did to the software market,

Any person can get a Linux source dump and compile it. Do you think anyone can download a Verilog file and make a custom ASIC on the kitchen table?
As long as the tech to build the chips and actually make silicon is in the hands of extremely expensive machines the owners of those machines can do whatever they want. And this is not going to change.

Yes, you can use FPGA but if you think you can buy an FPGA with the same firepower as your average Intel or AMD Desktop chip you are going to have a very complicated conversation with your bank manager. The FPGAs that can do this literally costs several ten of thousands of dollars. Per chip.

> d like to know what those improvements are.

For one thing, RISC-V does not have branch delay slots. They also took out any flag registers, but this is arather controversial choice, the ARM designers think this is nuts. RISC-V also tries to bring back the old vector processor idea of Cray as opposed to SIMD instructions although I don't think this has been implemented much.

One thing that RISC-V banks on is instruction fusion in the pipeline. This is one reason they ditched status flags, and several instructions were explicitly designedd to allow for this.

RISC-V is also designed from day one to be modular, there are multiple versions of the instructions set and a embedded designed can use
a very simple core for embedded on on-die jobs.

As for improvements over ARM, RISC-V (or MIPS) does not have the ability to just set the Instruction Pointer as a register, which wreaks havoc with branch prediction. ARM also has a conditional execution flag that is a bit of a controversial issue in CPU design world.

> Also, is there a critique of currently available RISC processors (ARM vs. RISC-V vs. SPARC v9 vs. POWER) available somewhere?

There is a good book about the architectures at that time, can look it up. Look on the internet, there are a few critques.

SPARC's main problem is the very deep and complex multiple-sets of registers which make threading a problem as far as I remember.

RISC-V is NOT A CPU DESIGN. It is an design for an instruction set and a rather simple one to boot. There are quite a few
designs for RISC-V chips in Verilog on GitHub and a really good tutorial (look for Bruno Levy). None of these are official,
all of them are open and all of them work. I have programmed RISC-V designs on FPGAs I got on GitHub. It is reall not all
that hard to design one.

You can buy the book with the specs in any bookshop and read it on the Internet, it is just an architectural description,
basically MIPS redesigned by the original MIPS team or David Patterson and his students which has been cleaned of
warts and lessons learned over the last 30 years. Even MIPS stopped making MIPS and now only do RISC-V because
it is very similar in any case.

MIPS is a tech the Chinese have had for years, every seccond router has a IPS chip in it, and the Chinese already build them. They
already have the lead on implementations of RISC-V chips, you can almost buy a 16 core desktop machine for $1500 and embedded
RISC-V is going places. All made in China.

As an aside, The RISC-V Reader, is a very good piece of documentation. No fluff, just the facts, very clearly written.

What is there to limit?? Any decent Chinese EE student can build one and if the specs are denied they would just
design a similar chip. None of this is brain surgery. Implementing it on 3mm ASIC IS brain surgery, this is what the
government should look at.

Apple used to have or still have a PCI card with a FPGA for video encoding. The compressor could reconfigure the FPGA for the Codec used for a specific job.

If you the time to figure and maintain this to do some contract work instead you can buy a wall full of 34" 4K monitors with the money. And have some left for beer.

I tell you what will make more productive. Most monitors have multiple inputs and a stupid fumbly way of menu diving to switch them. All I want is ONE BUTTON PER INPUT FFS. It is not relaly that hard, my dads TV from 1975 could do this. As, as for "automatic mode switch" Jesus no. When I reboot my computer or sleep my laptop to go grab a coffee and the signal goes down for a minute DO NOT CHANGE THE FRAKKING INPUT!!!!!

In Germany half the pools have co-ed changing rooms and you share the steam room after the gym with all the naked girls

This is a dick cracker not a nut cracker

That guy is well on his way to winning the Darwin Award!

Google runs a data center in the Arctic Northern Sweden in an old mine. How is this worse?

Better than the recent story of a Chinese data center that is under water