Comment A University Student's perspective on VHDL... (Score 2, Informative) 301
We were introduced to VHDL in our University's Digital Circuits course.
Most of the above commenter's have mentioned that Verilog is C like, I personally have never used or programmed in Verilog so I can't comment on that.
I did however like VHDL very much, particularly because it was *different* from C, I'm kinda growing tired of C like languages and VHDL was a breath of fresh air. It made FPGA's and the entire course in general a whole lot of fun.
It's strong typed nature was a bit cumbersome at first especially with converting std_logic to std_logic vectors and such because we weren't really shown how to do this or given a syntax/library reference like MSDN or Java's Documentation site.
So I'd say make a good introduction to Entities, Ports and Architectures, explain Process, Signal and Constant statements very well, also particularly highlight the strong typed nature of VHDL.
I think most of your students (such as myself) will not have done any programming in a true strongly typed language before, so this will be bit of a shock, and getting those conversions will be frustrating. (I have been there, Googling really does not help all that much)
I hope your students get as much fun out of that course as I did.
Cheers,
filereaper.