First, we are working on this, and your patches are welcome.
https://github.com/sbourdeauducq/llhdl/wiki
https://github.com/sbourdeauducq/antares
FPGA companies are not as evil as you make them out to be. As a matter of fact, a large part of Xilinx's motivation about closing the bitstream is not to be evil, but to limit the damage that can be done from their (stupid and large) customers misusing the FPGAs. They still publish a lot and you might be surprised to learn, for example, that the ISE software has options to dump the complete routing graph of all Xilinx FPGAs as well as some raw timing characterization numbers. The information is there, but it takes more work to go looking for it than to sit on your ass bashing the FPGA companies - as most free software activists do whenever the topic of FPGAs arises. No wonder why so little open source FPGA and EDA stuff gets done.
Finally, Milkymist SoC and FPGAs lie at two different levels of abstraction. When you are using a traditional CPU, both the logic design (HDL) and the physical implementation system (ASIC cells, P&R tools,
...) are closed. When you are using Milkymist SoC, the logic design is open and the physical implementation system is closed. The logic design is portable, and ported, to other technologies. I think we all agree this represents a progress.