paleshadows writes: In the company's blog, Sean Koehl, technology strategist for Intel, said that eight technical papers would be released this week, describing key findings from the company's work on future programmable multicore architectures. Koehl then provides a short preview: One of the papers discusses "data center-on-a-chip" (tera-scale processor composed of 32-core, each with 4-SMT, amounting to 128 threads of execution), proposing a new high-bandwidth L4 cache optimized by a cache quality of service discipline that will determine how multiple threads share cache space. Two other papers are about how to obtain parallel scalability for multimedia and search/mining applications. Another paper argues Intel would be required to build the memory directly on top of the die to obtain high-enough bandwidth to keep all threads busy. A related paper explores how caches would be shared between cores with an on-die interconnect mesh. Finally, two more papers discuss how Intel plans to simplify parallel programming using special runtime environments of tera-scale platforms and accelerator cores.
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