Nom du Keyboard writes: In Processor Whispers — About latencies and compilers Andreas Stiller opines on released information that AMD Bulldozer integer cores are less capable than their K10 predecessors. "The Bulldozer's integer core has only two instead of three ALUs (EX0, EX1). In exchange, it comes with slightly enhanced AGLUs (address generation logical units). Besides, the throughput specifications would draw attention to the fact that the Bulldozer's integer cores each have one pipeline less than the integer cores of its predecessor K10, although AMD boldly draws four pipelines into its block diagram – as the scheduler can now support the two ALUs (EX0 and EX1) and the two address generation units (AG0 and AG1) separately, whereas before these units were jointly operated by glued-together micro-operations. Still, this is no serious compensation for the three capable ALUs that the K10 and the competition's Sandy Bridge feature, as the two AGUs can only offer very limited aid – apparently, they can only participate in calculations related to the instructions CALL and LEA." Is AMD, once again, about to disappoint?
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