A Generic PCI Based FPGA Coprocessor? 34
graveyhead asks: "Inspired by a recent Slashdot article, I came across this fantastic package from the fine students in the Configurable Computing Laboratory at BYU: JHDL, which is a set of open source FPGA CAD tools. I am writing a proposal for a prototype system and I have a requirement for a 32 or 64 bit PCI card compatible with JHDL. I do not require any IP cores (which Xilinx seems to want to sell me hundreds of 'em), since our project uses its own custom cores. Also, I will not be building additional hardware around the FPGA processor, so the package needs to be fully self-contained. I simply need the ability to use JHDL to program the FPGA device over PCI under Linux, execute my circuit with parameterized values, and return the result. I found these boards, but I'm not sure which is appropriate or compatible, or if there are better alternatives that I am not finding in a similar price range (up to USD2000). Preferably, I want a chip with lots (1-10M+) of programmable gates."
Re:generic coprocessor? (Score:4, Informative)
Even if they weren't, programming a maths coprocessor is very different from programming an FPGA, and the things you can do are very different.
An FPGA is a programmable logic circuit, and you can connect almost any kind of digital electronics to it. From flashing lights to memory to network interfaces to bus interfaces (like PCI and USB) to whatever else turns you on.
Multitasking and resource locking (Score:3, Informative)
Suppose you had a nice 10 million gate FPGA on your PCI bus. Now, if you program it to do one thing and one thing only, then there's no problem. So if that FPGA set up to be a hardware DiVX encoder and that's it, all is well.
But let's suppose that you fire up your video editor, and it wants the FPGA to be a DiVX encoder. Then you fire up SSH, and SSH wants the FPGA to be an encryption engine.
It is currently VERY hard to dynamically reprogram sections of an FPGA (some do support partial reprogramming while running, but not all). It is also very hard for the hardware compiler to merge tasks - you would have to re-generate the layout of the FPGA each time you added a function.
What we need is the equivilent of a malloc() call to allow a single large FPGA to be used by multiple applications at the same time (until you run out of gates).
Once that exists, then you will see vendors making generic FPGA accelerators.
Until then, FPGA boards will be the province of a very few people, and prices won't come down very much, I fear.
Hey...heads up! (Score:3, Informative)
Contains a BIG listing (updated at the end of last month) showing boards and prices when available. Also lets you know if it's a PCI board or whatever.
I really doubt you will need a million or more gates. What are you trying to do, physically model a barrel of quarters? Is your code going to be as complex as a late-model Pentium?
To start out with, a 600kgate SpartanIIE-ish chip will have lots of room and won't break the bank. A mega-gate Virtex, on the other hand, will eat into your budget requirements for the chip alone.
But check out that link and you'll probably find something.