The dirty secret is that there aren't really any truly CISC CPUs any more.
For processors based on x86, the ISA may be CISC, but the execution of that isn't.
The instruction stream is converted to something RISC internally.
Recent-ish x86 CPUs are all basically "hybrid" processors in that regard.
It's not a "dirty secret", it's not a secret at all. People don't know it, but that doesn't mean it's a secret.
Also, the internal architecture of x86 processors is not "something RISC", it bears no relation to RISC. Interestingly, modern RISC processors are also designed this way, yet why would they be if they were already "RISC internally"?
RISC means "Reduced Instruction Set Computing". It was a philosophy that said that processors should be designed such that the logic that makes them is committed to th
A large fraction of a modern CPUs die is cache and memory hardware. The issue is that it might be possible to build a x86 CPU that consumes 200mW and gets a really good CoreMark score. However, once a huge cache is attached to the x86 CPU, then the 200mW power consumption number may go to pieces. The cache is often needed for real-world performance. With modern fabrication processes, every transistor has a certain amount of leakage current. For large caches the leakage current becomes a limitation on m
Or else right after we switch over everything to ARM .. they'll be like "Psych!" and switch to RISC V. No thanks.
The dirty secret is that there aren't really any truly CISC CPUs any more. For processors based on x86, the ISA may be CISC, but the execution of that isn't. The instruction stream is converted to something RISC internally.
Recent-ish x86 CPUs are all basically "hybrid" processors in that regard.
It's not a "dirty secret", it's not a secret at all. People don't know it, but that doesn't mean it's a secret.
Also, the internal architecture of x86 processors is not "something RISC", it bears no relation to RISC. Interestingly, modern RISC processors are also designed this way, yet why would they be if they were already "RISC internally"?
RISC means "Reduced Instruction Set Computing". It was a philosophy that said that processors should be designed such that the logic that makes them is committed to th
A large fraction of a modern CPUs die is cache and memory hardware. The issue is that it might be possible to build a x86 CPU that consumes 200mW and gets a really good CoreMark score. However, once a huge cache is attached to the x86 CPU, then the 200mW power consumption number may go to pieces. The cache is often needed for real-world performance. With modern fabrication processes, every transistor has a certain amount of leakage current. For large caches the leakage current becomes a limitation on m