Can anyone supply a concise explanation of the differences and how it's all done? I'm guessing we're talking about people drawing circuits on acetate or similar and then it's scaled down photo-style to produce a mask for the actual chip?
CPU code is in RTL,verilog,VHDL, whatever-- it's in HDL. Usually these days a synthesis tool or compiler will create chip layout that implements that HDL description in standard cell logic. The standard cells are latches, NAND gates, buffers, SRAM, etc. A software tool will place and route standard cells to implement the HDL in silicon, and then iterate on timing to make sure it's fast enough. Humans don't directly do the placement of standard cells, or route wires between them. In terms of photolithography, the standard cells are the silicon transistors, and the first two levels of metal.
It looks like they're making a mountain out of the fact that the standard cells were placed by hand here, and some of the more regular and important wiring was perhaps done by hand, too. You can often take your human knowledge of where the likely performance chokepoints are and place those carefully, and you can also take your human knowledge of where the wiring congestion will be, and be careful there. You're also perhaps able to wire things a bit more creatively in that you can use wrong-way metal and perhaps less gridding. And then you can still probably tell the algorithms to take care of the rest.
In either case the standard cells themselves are often handcrafted in CAD tools, but sometimes different layout software will make them, too. It's just that with large logic chips, past that point humans are often only in the physical design loop to take care of problems the tools can't solve independently-- like massaging things that come out of synthesis too slow to meet the targeted performance, or mandating certain metal levels will be dedicated to a clock mesh. Sometimes that human intervention is just permitting the tool to suck up more power by using faster standard cells. Other times it would be revisiting the architecture in HDL, but then again throwing it over to a computer to place and route. The humans are not actually moving cells around the chip in a CAD tool.
I don't do the synthesis part of the process myself, so someone can clarify or correct me. The thing I wonder about is why the chipworks guys assume hand placement necessarily takes much longer? Looking at the layout, I'd assume the biggest tradeoff is the size of the core, not time spent on placement. It's routing a gazillion non-regular wires that is hard for humans, not placement. We can still place standard cells in a core without needing years of time, provided it doesn't need to be perfectly area-efficient.