I had this idea for an FPGA design back in 1981... after reading Gilder's call to waste transistors... and I wonder if you think it might be worth doing even today? I believe that the design space for FPGAs may not have been adequately explored, and as a result we're all living with sub-optimal solutions.
It's very simple.. an orthogonal grid of 4 input, 4 output look up tables, wired to look like RAM to a host, and connect such that each output bit goes to one neighbor, and each input comes from a neighbor. Any logic function can be implemented in this manner (like all modern FPGAs). They could be clocked in A/B/A/B over B/A/B/A to eliminate race conditions, deadlocks, etc.
Bad cells could be routed around almost trivially... the big waste of course, is that without any dedicated routing fabric, all cells in the path of a given bit of data would have to handle it... and the propagation times would be long... but consistent. The advent of memristors makes this an extremely interesting idea to me, once again, as they make LUT costs almost zero.
So.. worth pursuing at all?