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Comment: Incorrect. (Score 1) 140

by glosalalia (#15632047) Attached to: Intel Pushes Back with Xeon 5100
As of the recent Analyst's Day announcements, AMD is moving to a largely modular design philosophy for the release of K8L and successive chips. The point of this move is to make alterations like the recent adoption of a DDR2 capable memory controller easier to accomplish, especially given the possibility of off-die and off package components like HTX coprocessors. I am not an electrical engineer and don't claim to fully understand how the interconnects work, but what I do understand seems to imply that AMD is moving in the direction of having and end to end implementation of HyperTransport that connects anything that sits before the Northbridge. They also seem to be aiming for agility of design, not stagnation.

Out of curiosity, what's so efficient about an architecture that bounces memory requests out to the off-die memory controller and then back to one of multiple cores every time each of the processors (which are sharing a single bus) needs something that isn't in cache? Similarly, how is the Intel choice more efficient than a cross-barred, shared cache solution that was engineered from the beginning to scale to multiple cores?

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